Labview 2011 FPGA Compile Error

Hi,
I'm new to FPGA. I want to use Labview 2011 SP1 with the Spartan 3E starter kit from Xilinx (Spartan 3E driver available from NI labview website).
I'm trying to work my way through the examples that came with the driver. I've run into the same compiler error with a number of the examples. The error is attached.
Error 7 occurred at Read from Text File in niFpgaCompileWorker_CheckForErrors.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:1
Possible reason(s):
LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.
C:\NIFPGA\compilation\Shift_FPGATarget_Shift_87E8371C\Spartan3EStarter.bld
I've checked the registry to ensure that the path to the compiler is correct.
Any assistance would be welcome.
Regards,
James.
Attachments:
Labview2011_FPGA_CompileError.JPG ‏96 KB

Hi,
I don't have any Xilinx tools installed - other than the ones that installed with the Labview FPGA module.
I have attached the compilation logs and output results from my attempt.
I have renamed the extension on the following files from .lvtxt to .txt
BuildResults.txt
CodeGenerationResults.txt
Regards,
James
Attachments:
BuildResults.txt ‏5 KB
XilinxLog.txt ‏42 KB

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Hello,
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-->
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Attachments:
XilinxLog.txt ‏80 KB

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-->
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Say hello to my little friend.
RFC 2323 FHE-Compliant
Solved!
Go to Solution.

I am currently attempting a compile after changing some things.
Just a side question. Is this particular to the Reinterpret node or are other "pink nodes" also affected by this? If I don't connect the output of a high throughput add, will it result in the same behaviour?
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Say hello to my little friend.
RFC 2323 FHE-Compliant

FPGA compile error

Good Afternoon,
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Message Edited by Mellobuck on 02-17-2009 09:51 AM
Data Science Automation
CTA, CLA, CPI
SHAZAM!
Solved!
Go to Solution.
Attachments:
FPGA error.JPG ‏63 KB

Xilinx doesn't support a depth of 1. If possible
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Fpga compile error Port width mismatch

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Details:
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1738 Infos, 30 Warnings, 2 Critical Warnings and 14 Errors encountered.
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while executing
"source -notrace {./.Xil/Vivado-9588-/realtime\toplevel_gen.tcl}"
invoked from within
"synth_design -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full""
(file "C:/NIFPGA/jobs/Riuys15_TD5ekmx/synthesize.tcl" line 25)
invoked from within
"source "C:/NIFPGA/jobs/Riuys15_TD5ekmx/synthesize.tcl""
# exit
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I am not sure what the error is all about. Could someone help me?

It's usually better to take a look at where the code failed to compile in the process than trying to read through those logs. In future cases, you'll want to show that information as well.
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Hello everyone !
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Attachments:
error.jpg ‏71 KB

Hi Jaffer,
It looks like you have all the right software installed for this compilation so I dont think that is the problem. Are you compiling your own code? Could you try a blank VI or an example for the 7851r? If the examples work then please post your project zipped together so I can view what may be going wrong. If you cannot compile a blank VI then please post a MAX technical report so I can confirm that you have all the software you need installed on the system.
MAX Tech Report:
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Solved!
Go to Solution.
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errorfpga.PNG ‏42 KB

Hi Prashat,
The error displayed is clear.
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FPGA Compile Error: Timing Violation

All,
I've got an issue here I've been struggling with for a couple days now. I'm trying to implement a very watered down Kalman filter in the FPGA (I wanted it to run faster than I had it running in the RT.) After quite a bit of optimization, I'm still stuck to no avail. This first thing I tried was simply using the filter I had and changing my math to use fixed point instead of floating point. However this was about 20 operations in series (multiplies, adds, subtracts, and one inverse, (( what's the most efficient way to do an inverse in the FPGA? ))) and the FPGA did not like that at all. So I tried to pipeline the operation. Now mind you this isn't a true pipline because new data cannot be introduced to the pipe in each cycle (I need the output of the last cycle before I can introduce new data,) but I was simply trying to split up the math and have the FPGA only do part of it on each iteration of the while loop, because I thought the FPGA would be able to run this filter way faster than I needed to.
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Status: Compilation failed due to timing violations.
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Device Utilization
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Flip Flops: 28.5% (11692 out of 40960)
Total LUTs: 45.9% (18788 out of 40960)
Block RAMs: 0.0% (0 out of 40)
Timing
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Actual Xilinx Options
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Map Overall Effort Level: High
Place and Route Overall Effort Level: High
Start Time: 6/6/2010 10:11:47 PM
End Time: 6/6/2010 10:57:33 PM
And then when I try to investigate the timing violations the "Timing Violation Investigator???" gives me this!!:
Possible reason(s):
An internal error occurred. Please try again or contact National Instruments.
Details:
Error Code --> -61499
Error Text --> <APPEND>
Additional Information: There is no matching tag in Xilinx twx file
There is no matching tag in Xilinx twx file
Also,
I was able to successfully run the "Timing Violation Investigator" a couple times. The first time it pointed to a multiply operation which i replaced with high throughput math and pipelined. The second time it pointed to "non-diagram components," how am I supposed to fix that?
I've attached the code and the xflow.log! Thanks for your time!
Thanks!
Ken
Attachments:
FPGA.zip ‏778 KB
xflow.txt ‏1138 KB

Hey Ken!
If you hit the "Investigate Timing Violation" button and go to the analysis page, it looks like there are a couple of math functions that are taking longer than expected.
If you replace them with high-throughput math equivalents (from the FPGA Math & Analysis palette) and manually configure the inputs and output FXP word/integer lengths, you might be able to get them within the timing requirements.
Let me know if that works!
Caleb Harris
National Instruments | Mechanical Engineer | http://www.ni.com/support

FPGA Compile error on remote compile worker - but not on local!?

When i compile using Rebuild for building my VI to FPGA on NI cRio-9082 I get this:
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*** glibc detected *** /usr/local/natinst/NIFPGA/programs/xilinx13_4/ISE/bin/lin/unwrapped/trce: double free or corruption (!prev): 0x09fd05e0 **
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-Nick-
Nick C | Staff LabVIEW Platform Product Support Engineer | National Instruments

Labview 2011 FPGA Compile Error

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