Layout generation with VSS

Question

Hello all,
I am in the process of designing a phase locked loop based frequency synthesizer. I successfully simulated the PLL. The PLL chip was simulated using the Phase frequency detector/charge pump and the divider provided in VSS element browser. For the VCO, I used the behavioural model, again in the element browser. The loop filter was simulated in MWO using discrete components.
My problem is this. I am trying to generate the entire layout within Microwave Office Design Environment. How can I assign artwork cells (footprints) to the PLL chip and the VCO? I can create the footprint, but so far unsuccessful in attaching to a component (in VSS). The alternative is doing the layouting using a separate layout package. But I am trying to do everything (including routing) within VSS as VSS seems to be capable of analyzing the effects of traces and trace coupling etc using ACE and AXIUM.
I found a very interesting video in the AWR/Ni short video series, which is very relevant to this question. The particular one I am referring here is PCB Design Part 4: PCB trace design. This video is on a VSS simulation accounting the trace effects as well. Unfortunately, the video focuses on the simulation part and does not address my problem. In this video, they have attached a foot print to a non-linear power amplifier model created using VSS. Apparently, there is a footprint attached, but the video does not show how it was done. Your help is greatly appreciated.

Answer 1

VSS system diagrams do not include layout.  Layout, including footprints, is part of circuit level design (Circuit Schematics).  You can create a circuit schematic and its layout to describe your interconnect, simulate the circuit using the circuit simulator or EM, and then use that circuit schematic as a model of the interconnect in the top level system diagram as a LIN_S block.