Logic 9 in 64 bit

Hello.
Can anyone answer me a few questions, the manual and google aren't really helping me much
Is Logic 9 automatically set to 64 bit, even though my Mac boots only on a 32 bit Kernel? i did the get info on the App icon and it only states to use in Rosetta not to go back to 32 bit as described.
Also, i am looking in to potentially getting a new laptop which i believe will have 64 bit capabilities, as all do now? if i was to be making tunes on my 64 bit laptop and wanted to do a mix say on my 32 bit desktop, would it make any difference whatsoever provided i was working on the same sample rate?
Sorry for sounding a bit dumb
Cheers

Matt Wice wrote:
Is Logic 9 automatically set to 64 bit, even though my Mac boots only on a 32 bit Kernel? i did the get info on the App icon and it only states to use in Rosetta not to go back to 32 bit as described.
That's odd. It defaults to 32 bit, but you should be seeing the option in the Get Info window unless you are on a machine that isn't 64 bit or 10.5. And your sig says mac pro and 10.6.2, so your OS is running in 64 bit. What does Logic say in the About Logic Pro window, 32 or 64?
Sessions should transfer between 32 and 64 bit machines without any problems, the only issue would be if a session on 64 bit used more memory than the 32 bit version can handle.

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danseq wrote:
Even prior to 9.1 h.264 was not recommended for use with Logic, as it takes a great deal of Logic's resources to convert it on the fly. Glitching and stuttering is to be expected.
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Mac Pro 3,1 (early 2008), 8-core 2.8Ghz.
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4 SATA HDDs
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Steinberg UR22 audio interface (USB)
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Could be corrupted preferences.
In the Finder, choose Go > Go to Folder from the menu.
Type ~/Library/Preferences in the "Go to the folder" field.
Press the Go button.
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http://support.apple.com/kb/HT3989
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hey over there,
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Message was edited by: Hi I'm A Mac

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...anybody?
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Hi there jdtay2,
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Processor Name
32- or 64-bit
Intel Core Solo
32 bit
Intel Core Duo
32 bit
Intel Core 2 Duo
64 bit
Intel Quad-Core Xeon
64 bit
Dual-Core Intel Xeon
64 bit
Quad-Core Intel Xeon
64 bit
Core i3
64 bit
Core i5
64 bit
Core i7
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Logic Pro and MainStage 64-bit mode FAQ
http://support.apple.com/kb/ht3989
-Hope that helps,
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Vivado 2015.2: Simulation and synthesis reverse bit order of std_logic_vector in logical operators

In both simulation and synthesis the logical operators on std_logic_vector bit-reverse the operands in the result, at least in the case where the result of the expression is passed to a function.
I suspect this issue applies to other operators as well, though I have only tested the problem with the logical operators. I also suspect the issue exists in other situations where a function is not involved.
This is incompatible with both ModelSim simulation and XST synthesis and it breaks a lot of our code.
The attached xsim7.vhd example shows the issue. The xsim7.tcl script will run the Vivado simulation. Under Windows, the xsim7.bat will run the whole thing. The xsim7.xpr project file allows synthesis under Vivado, and you can look at the schematic to see the issue in the synthesized netlist.
The source module also simulates under ModelSim and synthesizes under XST, and these show what I believe to be correct behavior.
Can someone please verify this error and either file a CR or tell me to file an SR?
Ian Lewis
www.mstarlabs.com

Hello Bharath,
When I said "what was index 'LOW becomes index 'HIGH" I meant the 'LOW of the source operands and the 'HIGH of the result, independent of the actual index range. I would have no problem with any 'HIGH and 'LOW on the result of the operator as long as the direction matched the left source operand, though personally I would prefer the same 'HIGH and 'LOW as that of the left operand.
Looking at the IEEE implementation of logical "or" on std_logic_vector from package std_logic_1164: https://standards.ieee.org/downloads/1076/1076.2-1996/std_logic_1164-body.vhdl:
-- or
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
the operator does exactly what Vivado seems to be doing: alias the downto source vectors to a to range of 1 to 'LENGTH and then return a vector of 1 to 'LENGTH. This both bit reverses the downto indexes (the alias on the source operands does that) and changes the range to "to" with a 'LOW value of 1.
This gives us the 'LEFT 1 and 'RIGHT 4 we see.
So far, I have found no definition from IEEE of what logical operators, such as "or", are supposed to do on std_logic_vector except as defined by this piece of code for "or" and the other operators' associated bodies from the std_logic_1164 package.
What this code does seems like a horrible decision about how to implement the logical operators on std_logic_vector with respect to range direction, but it is compatible with what Vivado does, and incompatible with what XST does. (I had never investigated this issue before because what ModelSim and XST did made perfect sense to me.)
That the assignment (Result := s) works as expected, makes sense. The assignment of the "to" range s to the "downto" range Result maintains the 'LEFT relationship. That is, Result'LEFT (index 3) receives s'LEFT (index 1). So, the bits are reversed a second time.
That ISIM does not match what XST does seems like a defect no matter how you look at it. Your simulation can never match your synthesis if you care about the range direction inside a function (and I suspect in other places too). This deserves an SR or CR if you are still doing any work on those two tools. I think you may not be.
Are you able to find out whether Vivado was changed from XST on purpose with respect to the behavior of logical operators?
If this is "as designed" then I have to start working on updating our code to live with it. But, if this is something that happened by accident, and you will change Vivado to match XST, then I probably want to wait. Updating our code to live with this behavior is going to be a pretty big job.
Thank you for your help,
Ian

Logic 9 in 64 bit

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