LV FPGA XYmultiplot error

Hi guys,
First of all, this is a bug report, and not a question. But I wasn't sure where to put this on the website or forum so I put it here. If this does not belong on the forum, please feel free to remove this post and send me a message where I can put this in the future.
This is the error I get when using a multiplot XY-graph:
An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:
Error 1055 occurred at Property Node in nirviObjectToResholderInfo.vi->nirviMakeLineInfoSubTagsForDiagramObjectRef.vi->nirviMakeTreeLineInfoTagForDiagramObjectRef.vi->nirviDiagramObjectError.vi->nirviSplitRegisterListBySize.vi->nirviPrintOneClkFramework_bushold.vi->nirviGetImplementation___busholdModGen.vi->nirviGetImplementation___busholdModGen.vi.ProxyCaller
Possible reason(s):
LabVIEW: Object reference is invalid.
and the code you'll find in the attachment. The issue is solved when I use 2 separate waveform charts for the two signals instead of 1.
Best regards,
Dries
Attachments:
lv code xy-multiplot.png ‏17 KB

Hello Dries,
Thank you for taking the effort and bringing this to our attention.
The error you were seeing is not a bug. It's the build array function in the screenshot which is trying to create one big array which most likely does not fit the FPGA.
Depending on the size of the FPGA on your device, the maximum array size will be limited accordingly.
If the workaround which you found yourself doesn't suffice, decreasing the total size of the array will also most likely make the error go away.
Please let me know if any questions remain.
Kind Regards,
Wouter
National Instruments, Northern Europe

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Fpga compilation xilinx error 'Process "Map" failed' - 'unroutable situation'

When I try to compile a Labview fpga project on our new system, it fails with the following error summary (the full Xilinx log is attached):
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:LIT:536 - IBUF symbol "aUserGpio<1>_IBUF" (output
signal=aUserGpio<1>_IBUF) has the attribute IOBDELAY set to value NONE and it
is driving an IODELAY. If the IOBDELAY attribute is on the driving PAD, it
has precedence over the IBUF one. Either the constraint or the design need
modification to prevent an unroutable situation.
Errors found during logical drc.
Design Summary
Number of errors : 1
Number of warnings : 349
Process "Map" failed
Start Time: 10:31:49 AM
End Time: 10:55:32 AM
Total Time: 00:23:43
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
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NI FlexRIO Adapter Module Support 2.2.0
NI-RIO 4.0 (FlexRIO 2.1.0)
Xilinx DRAM compilation bug fix patch from NI article id 5E4FNCDP
Xilinx clock bug fix patch from NI article id 5GFAB7DP
replaces c:\NIFPGA\programs\Xilinx11_5\ISE\xilinx\lib\nt\libPlXil_Clocks.dll; The installed version is c:\NIFPGA\programs\Xilinx12_4-> Manually copied the dll to the installed version
The Project uses the 5761 low speed clip and a DRAM FIFO.
I tried to compile it before installing any patch, after installing the DRAM patch, and after installing both patches and always got a Xilinx error after ~10 minutes compile time. The error summary shown above and the attached Xilinx log are from compiling with both patches installed.
It compiled correctly on our older system:
Hardware:
NI PXIe-1082 Chassis
NI PXIe-8133 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview2011version10.0.0
LabviewFPGAmodule10.0.0
FPGAcompilationtools (Xilinx11_5)
NIFlexRIOAdapterModuleSupport2.1.0
NI-RIO3.5.1 (FlexRIO1.5.0)
XilinxDRAMcompilationbugfixpatchfromNIarticleid5E4FNCDP
Any help / suggestions greatly appreciated,
Fabrizio
Attachments:
XilinxLog.txt ‏1482 KB

Hi Torpedotown,
Can you tell me what version of FlexRIO Adapter Module Support you are using?
The 5761 Low Speed CLIP has a constraint that doesn't work properly with some versions of the compilation tools. In order to solve this you should be able to upgrade to our latest version of FAM support, or go change the constraint manually.
For the latest version of FAM support, go to http://ni.com/info and enter code "famsoftware"
If you've modified constraint files before and feel comfortable doing it yourself, let me know and I can provide you with the details on how to do that.
Thanks!
National Instruments
FlexRIO & R-Series Product Support Engineer

FPGA Internal software error

Hi,
I'm using labview 2009. When I compile the fpga target vi, i got the following message:
" An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:#,910x,907x,911x,783x;781x,785x;784x,910x,907x,911x,783x;781x,785x;784x,9101;9102;9103;9104,9072;9073;9074;9144;9601;9602;9611;9612;9631;9632;9641;9642,9111;9112;9113;9114;9116;9118,7830;7831;7833;7811;7813,7851;7852;7853;7854;7841;7842,9101;9102;9103;9104,9072;9073;9074;9144;9601;9602;9611;9612;9631;9632;9641;9642,9111;9112;9113;9114;9116;9118,7830;7831;7833;7811;7813,7851;7852;7853;7854;7841;7842,Onboard,Onboard,Onboard,Onboard,Onboard,Derived,Derived,Derived,Derived,Derived#,,,,,,,,,,CONST_TCO_SPI,12.5,13.5,11.25,14.5,12.25,9.25,13.5,7.5,11.25,8.5CONST_TSU_SPI,2,4,3,2,4,4,4,4,4,4CONST_TH_SPI,4,4,4,4,4,4,4,4,4,4CONST_TSU_PLUS_TH_SPI,6,8,7,6,8,8,8,8,8,8#,,,,,,,,,,CONST_TSU_SSMISO,6,6,6,6,6,6,6,6,6,6CONST_TH_SSMISO,4,4,4,4,4,4,4,4,4,4CONST_TSU_PLUS_TH_SSMISO,10,10,10,10,10,10,10,10,10,10#,,,,,,,,,,CONST_9201_TCO_SPI,10,10,10,14.5,12.25,9.25,10,7.5,11.25,8.5
Method Name: <b>Compile For Target</b>"
Does anyone know what caused this problem? Thanks in advance.

Hello Kb1126,
To better be able to answer your question could you please share what RIO device you are working with, the RIO device software and any relevent Xilinix tools versions, as well as the possible version installed on your RT target (assuming you are using a RT controller to interface with your FPGA).
Thanks,
Blayne Kettlewell

FPGA 2010 Compilation error - TclTasklC:project_028: Unknown property value

Hi, I'm using a cRIO 9075 and a NI 9211 to measure temperature for a project busy with. Everytime I try t compile code I have a compilation error that read as follows:
Compilation failed due to a Xilinx error.
Details:
ERROR: TclTasksC: project_028:Unknown property value "spartan6" specified for "PROP_DevFamily"
Can someone help me on how to resolve this error, I'm using LabVIEW FPGA 2010 and Xilinx 11.5
Regards
Solved!
Go to Solution.

What version of the NI-RIO driver do you have?
Attached is a chart with the different compatibilities of the RIO driver.
NI-RIO and LabVIEW Version Compatibility
http://digital.ni.com/public.nsf/allkb/577CC9A7DCFC73DF8625738400116CC3?OpenDocument
Is this a 64-bit machine? Also, the minimum version of LabVIEW that will work with the 9075 is LabVIEW 2010SP1. You can verify if you have this version by going into Measurement & Austomation Explorer and expanding software. If you do not have LabVIEW 2010SP1, you will need either the platform DVDs for 2010 SP1 or you can download the content from www.NI.com/src.
You will also want to verify that you have the 2010SP1 FPGA module and 2010SP1 RT module.
Also, does this issue occur with all FPGA VIs that you try to compile or only the one that you are currently working on?
You can check by doing two things:
1. Try to compile a blank FPGA VI (i.e. nothing on the block diagram or front panel)
2. Try to compile an FPGA VI from one of the example LabVIEW projects
Please post back if one of these troubleshooting steps resolved your issue or if you're still having problems.
Jordan

Fpga compile worker error (file not found)

Hi
I try to get started with the FPGA functionality of cRIO and got stuck. This seems to be no issue of the cRIO(9014) but of the Xilinx software together with NI.
I am running an English LV 2011 ( many previuos versions installed as well) on a German Windows XP prof. 32 bit.
I was setting up a little project and when it came to compiling ran into errors. First I asked a colleague than I checked the NI support web site. Next time I'll contact the NI local support, but maybe some of you guys hast a faster answer before.
1. I want to run a local compile server. I can start it from start> programs>NI> FPGA. Up pops a question whether I want to allow others to connect remotly. The answer seems to make no difference.
I do not see any icon in the task bar or elsewhere. SHOULD I see a process running in the task manager ?
2. The NI Service locator seems to be running http:/localhost:3580/dump shows a table like attached. SHOULD I see the server running here ?
3. If I start the Compile Worker after some seconds I get a message saying something like file not found. I think, compile server error is only a followup.
I have already re-installed the Xilinx-Tools from the down loaded iso. (that having started yesterday night ......) .
I attach as well the log file. (would have liked, but three is the max)
That whole system of compilation seems to be not very stable when I see all the posts, but I have not found these specific errors.
So I still hope someone has an idea.
Thanks in advance
Gabi
7.1 -- 2013
CLA
Attachments:
ServiceLocator.jpg ‏47 KB
XilinkNotFound.jpg ‏101 KB
FPGA Fehler.jpg ‏44 KB

Gabi Tillmann wrote:
Second thoughts:
Is it really worth using that so highly promoted FPGA on cRIO ???? We'll see.
This Question is technically wrong!
Whenever you are using the C-Series IO-Modules of the cRIO you are using the FPGA, even in ScanMode where NI RIO loads pre-defined bitfiles onto the FPGA.
The FPGA provides you ns Timing, it gives you nativly true parallelism, you are directly programming the bahaviour of FlipFlops, LUTs, Registers and so on.
It gives you the ability to programm hardware without the need to understand complex HDL languages.
The cRIO is besides PXI the most flexible and powerful (908x) platform NI offers. The decision to use an FPGA or to use a cRIO should not be "because it's there".
The decision to use an FPGA-based Platform depends on the complexity of the application, just think about custome beahviour of IOs or custom triggering.
Christian
P.s.: Great that you solved your compiler issue.

Fpga code generation error after updating from 8.5.0 to 8.5.1

Hi All,
I have a FPGA-VI which was compiled in LV 8.5.0 without errors. After I updated to 8.5.1 the Code Generation stops, telling me the clock domain is not supported for write FPGA I/O node (see attachment). Also I attached a picture of a simplified FPGA-VI which brings up the same error.
I use a PXI-7833R connected to a cRIO-9151 R Series Expansion Chassis with a NI-9421 modul (8-ch DI, 24V) installed in it.
My original FPGA-Code has a theoretical maximum of 22MHz, so I can't change the clock domain to 40MHz.
Do you have any suggestion how to get the VI compiled?
Uli
Solved!
Go to Solution.
Attachments:
ErrorMessage1.jpg ‏30 KB
FPGA-VI1.jpg ‏17 KB

Hi Ruhmann, hi Basset Hound,
thank you for your reply and giving me a better insight in things.
I started my VI with 40MHz clock domain. The Vi got bigger, some more logic here and some more code there. Finaly the compiler couldn't satisfy the timing any more. Instead of optimising the code, I reduced the clock domain.
Until your post I didn't realise I use CompactRIO I/O. Is There a difference to (let me call it) "direct R-Series I/O"?
I need the Expansion Chassis (Connector 1), the 9421 (8-ch DI) and 94?? (8-ch DO) to connect 24V logic to the FPGA. Additionally I have two SCB-68 (Connector 2+3) for 5V logic (DI, DO, A/B linear position measurement, pulse generation) and some analog input. All code in 1 VI, but distributed in 3 loops.
To change the clock domain back to 40MHz, I have to optimise my code . Well, the code is sloppy , so optimising is OK .
To tell the hole story:
After updating to 8.5.1, my first contact to NI was by phone. The engineer asked for the Code, the project and the hardware.
It took a while for me to put the information in an email. Meanwhile engineer the found a paper with the solution I
mentioned in my second post and send it to me, before looking at my code. The paper said someting about "tightend timing constraints",
"safe communication" and "multiple DMA target to host transfer". Not exactly what I was doing, but I reinstalled
RIO 2.3.1 and ... compile successful.
@ Basset:
The simple VI (picture) in my first post reproducese the issue exactly.
I'm not at work any more, so I can't provide the full code or the SRQ# until tuesday (holiday on monday ).
FYI I'm located in Germany, so I called the german NI support.
Uli

FPGA Compile Farm Error -61319

Hello,
I am having problems compiling FPGA code, I am getting error -61319 when the compile fails. Most frequently it times out during the "estimating resouces planAhead" stage and sometimes in the synthesis stage. I am using:-
Labview 2012 SP1
Xilinx 13.4 Compilation Tool
Windows 7 with 2 GB of RAM
I have tried reinstalling the Labview FPGA Xilinx module, to no avail. I have tried compiling different projects that have compiled previously, with no success! I have compiled successfully with this PC previously, although I am not sure if I have since changing to 2012.
I have tried searching for information related to -61319 but all I can find is the error text that accompanies the fault code in the details window. Two images below show the error code I am receiving.
Any help/advise gratefully received.

Hi,
BODGER:
I'm sorry that you're still having difficulties! In terms of putting the 2011 back on RIO boards, that shouldn't be too much of a problem, you will just have to format them and reinstall the RIO 2011 software.
MATHIEU:
What do you mean by "open the compile worker"? On my machine, when I run the exe as you suggested, I just get a pop up saying "compile worker running" in the system tray; it should not open any kind of window.
BOTH OF YOU:
Please would you run me through, with screenshots, a step by step process of what you're doing to compile the VI, from the project to when you get the error? I've run out of information on the database as it is, so I'd like to take as much information as I can to our specialists to see if they have any ideas.
As I say, I'm sorry that you're both running in to issues and I will do my best to help you resolve these with the information which you give me.
Best wishes,
Chiara A
Applications Engineer with NI UK & Ireland

FlexRIO update fpga simulation libraries error

I downgraded to ModelSim 6.5c to remain fully compatible with niFPGA. I am now trying to generate simulation VHDL files and need to update my FPGA simulation libraries. When I do so, I get the following error:
"An error occured while updating the FPGA simulation libraries. Make sure ModelSim is installed correctly and the files in the ModelSim directory are not read-only."
Not the most helpful of messages. ModelSim is installed correctly and runs. All files in all subdirectories have read/write permissions. What is labview looking for that it is not finding? Maybe that will help narrow down the issues I am having.
Thanks in advance.

Hello again manjagu.
There was a Corrective Action Request (CAR) filed regarding this sort of behavior however, it indicates that there should not be an issue with 6.5c and LabVIEW 2010 SP1. I am curious as to if the problem may be a result of an artifact left by the installation of version 10 or 6.6d. Did you uninstall these versions completely prior to installing version 6.5c? One thing that might possibly work to remedy this situation is to remove the ModelSim environment variable from your system as that seems to be related to the issue. For information on modifying environment variables in case you are unfamiliar with this process, please reference the article below.
How to Add, Remove or Edit Environment variables in Windows 7?
Hope this helps.
Regards,
Michael G.
Michael G.
Applications Engineer
National Instruments
Self-realization: I was thinking of the immortal words of Socrates, who said, "... I drank what?"

Broken Wire ---- FPGA Interface Node Error

Hi there,
I am programming my RT application and I am getting this weird error:
As you see, I am trying to set the value to a FPGA control (which is a typedef enum) and I am getting this broken wire strange
for me, error.
I was looking for a solution in the forums but I wasn´t able to get one.. Anyone could help me??
Thanks!!
PS: The error message was like "The type of the sink is void" which is untrue because is already defined in the FPGA vi.
Solved!
Go to Solution.

Solved.
To who may concern, it was like I changed some of the typedefs and didnot have that in mind. A recompilation solved the issue.

FPGA Simulation ISim error

I'm looking to start simulating my FPGA Target in ISim and have run into an interesting error.
When I have built and exported the Simulation file (It runs in ISim although without a Testbench it doesn't show much).
When I try to write a LV VI using the Simulation VIs I get an error as shown below.
Is this functionality not supported for ISim? THIS Webpage seems to suggest editing the VHD Files is required for interfacing int his way which is really not very comfortable.
Can someone comment on this because information ont his topic is not exactly easy to find on the NI website. I have found that Xilinx has abandoned Modelsim so hopefully this functionality is (or will be) supported again.
Shane
Say hello to my little friend.
RFC 2323 FHE-Compliant

I know ISim can simulate but my problem is the difference between the two available ways of simulating.
One is to write a test routine in VHDL which, having written FPGA code in LabVIEW is really not comfortable at all. (This is possible with ISim)
The better of thwe two methods is to actually use LabVIEW to write the test code which then interfaces with the simulated hardware, allowing us to implement software for testing much more rapidly and also utilising actual project code.
At the moment this second version is only available using Modelsim SE (Which apparently no longer exists, it has changed names) which costs in the region of 20k Euros. Kind of makes LabVIEW look cheap.
So my request was if this second, far more comfortable method, would be possible to implement in Isim or if it already IS implemented but I have performed soem wrong action in tryint to get it to work.
Best regards
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Fpga compilation error

Hi all
I am developing the labview code for my application and I have faced the following problem:
I have a PXI system with 2 fpga cards (7854R and 7851R) for adquiring 13 fast analog signals. I finished the work related to the 7854R and everything was working OK. Now I am working in the 7851R, whose code is much simpler than the one in the 7854R. However, I cannot compile the fpga7851.vi. I got a error, that can be checked in the report attached. This VI can be compiled without problems when it is included in a new empty project, so I assume there is no problem in the VI itself. I have tried to set smaller FIFO and Data Buffers for this FPGA, but cannot compile either.
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Thanks in advance,
Regards,
Pablo
Attachments:
XilinxLog.txt ‏712 KB

Hi Pablo,
A comparison on numerical data types can be found here.
EDIT: My reply below was written to your post ‎2014-03-07 10:41 AM:
You are correct, it looks like the program you are synthesizing is to large for the FPGA. Could you please verify by deploying a smaller program?
One of the last entries in the error log states that
"ERROR:Map:237 - The design is too large to fit the device. Please check the
Design Summary section to see which resource requirement for your design
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There are some more information about the FPGA in the NI PXI-7851R Data Sheet, I have extracted the most relevant information for you below:
NI 7841R/7851R
FPGA type
Virtex-5 LX30
Number of flip-flops
19,200
Number of 6-input LUTs
19,200
Number of DSP48 slices (25 × 18 multipliers)
32
Embedded block RAM
1,152 kbits
You can always check the different Reports in the Compilation Status window for resource utlization information on your current project.
Best regards,
Robert P-F
Applications Engineer
National Instruments Sweden

Regarding SPATRAN 3E FPGA BOARD PROGRAM ERROR

Hello Sir,
I am new to FPGA family.I have SPATRAN 3E FPGA board and i am trying to simulate for an OR gate of 3 input and one output. While I am siluating the code, the following error is showing.
FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/precompiled.exe.sim/ieee/p_2592010699.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Please help me to solve this problem.

Hello,
Can you check the OS (Operating System) from the released notes of ISE (UG631) which you are using if its supported?
Also Try Cleanup the project files in ISE before running simulation:
Thanks,
Syed
Please mark the Answer as "Accept as solution" if the information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-----------------------------------------------------------------------------------------------

FPGA compilation error 1000

Today when I wanted to compile my VI, I got this error and don't know what the reason is and how to solve it. Next, I couldn't find anywhere on the forum / Google a similar case.
Does someone has an idea where it might come from and how to solve it?
An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:
Error 1000 occurred at an unidentified location
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Solved!
Go to Solution.

Hi Harlequinade.
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Wich LV version, OS and wich hadware do you use.
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Best regards
Bernhard Rennhofer, AE
National Instruments (Germany,Munnich)

Save for previous error on FPGA vi (LV2009 - LV8.6)

Hi all,
I have an RT project i want to back save from LV2009 to LV8.6. When trying to save for previous, all FPGA subVI's are saved correctly but the top level FPGA vi returns error 1536:
LabVIEW: To save a password-protected VI for a previous LabVIEW version, you must enter the password.
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I am getting the same error. LV 2009 on Windows Vista. There are only 4 VIs (FPGA Main, FPGA subVI, Host Main, Host SubVI) and a Shared Variable Library file. The SV library file and on the FPGA subVI get copied into the new directory along with the LVbit file but nothing else. I am not even sure what VI is having trouble on.
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How to synchronize two fpga DIO?

Hi!
I am using two FPGA 7962R (flexrio) with each 6581 terminal board in PXIe-1082 chassis. My problem is how to synchronize two 7962R digital output with PXIe-1082 chassis backplane signal Dstar* or Clk10 or DAQ signal.
Actually I tried the synchronization with one DAQ counter clock (confering 'Gen Dig Pulse Train-Finite_NI. vi') , and get the signal PXI-Trig0 by source terminal and target terminal connection, but that one does not work properly. Especially, one trigger signal in HOST to set the starting point of each FPGA (7962R), make error by depending on the trigger signal value(Hz value and Timed loop clock in FPGA vi). It was very tricky and not reliable. (I am attaching figure files as explaining the situation)
My aim is simply to use two FPGA 7962R Digital output as one FPGA, for controling X-axis, Y-axis with each FPGA, while able to change each FPGA (X-axis, Y axis) digital output value. Because the synchronization is not correct, X,Y axis control with Two FPGA currently is out of target if I use simply while-loop design in HOST and timed-loop design in FPGA vi. What is correct design to synchronize the two FPGA 7962R without using PFI line, only with PXIe-1082 chassis backplane signal and able to change the digital output value? Please let me know any idea for HOST vi, FPGA vi programming.
Many Thanks
Attachments:
host1.png ‏47 KB
fpga1.png ‏131 KB

Posted response to this in the following thread:
http://forums.ni.com/t5/Real-Time-Measurement-and/synchronization-two-fpga-7962r-digital-output/m-p/...
Patrick H | National Instruments | Software Engineer

LV FPGA XYmultiplo​t error

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LV FPGA XYmultiplot error