Master/Slave settings for HD and SuperDrive

i recently updated the hard drive to a 17" usb2 iMac flat panel, I upgraded the standard 80GB HD with a new maxtor 250GB disk, the problem is that the transfer rate from dvd/firewire/hd to hd are superslow.
what i don't know is the jumper settings for the two units, i used slave for the superdrive and master for the hard drive, is it possible that they go inverted?
thanks
g

I don't know if that's causing the low data rate, but Apple sets the superdrive to master and the harddrive cable select (see http://developer.apple.com/documentation/Hardware/DeveloperNotes/Macintosh_CPUs-G4/iMacNov03/index.html). I know from own tests that the 17" iMac G4 is capable of 50 MB/s for the internal HD.
Mac mini G4 1,42/512/80, PowerBook G4 12" 1,5/1,25/80 + 23" ACD Mac OS X (10.4.7) as well as iMac G4 17" 1,25/2/320, PM G3 DT 500/576/20 + 17" Syncmaster 710T

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hI
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pls let me know
regards
kumar

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I am attempting to duplicate the FPGA synthesis flow using XST and ACE to boot Solaris on a Digilent board. I encounter some steps, warnings, and errors listed below that are not covered in the documentation I have. In following section 6.2 of the DV Guide,
after first running
rxil -device=XC5VLX110 sparc
I opened the ML505 project that I found in the Release 1.6 location at $DV_ROOT/design/sys/edk/system.xmp using XPS 10.1 (required to be 9.1i or later), which updated the project (I believe from EDK 9.2 in OpenSPARC 1.6) to the current release, including some manual updates required to be made because of incompatible cores as described in file Version_Changes.log:
The following files will be modified:
system.mhs
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Core plb_v46 1.00.a will be replaced by 1.02.a
Core mdm 1.00.a will be replaced by 1.00.b
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XPS 10.1 ³ Hardware ³ Generate Bitstream
I get warnings and errors in the XPS log file:
Check port drivers...
WARNING:MDT - PORT:IWAIT CONNECTOR:ilmb_LMB_Wait -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 196 - No driver found. Port will be driven to GND!
WARNING:MDT - PORT:DWAIT CONNECTOR:dlmb_LMB_Wait -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 232 - No driver found. Port will be driven to GND!
WARNING:MDT - PORT:bscan_tdo1 CONNECTOR:bscan_tdo1 -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_b\data\mdm_v2_1_0.mpd line 197 - No driver found. Port will be driven to GND!
WARNING:MDT - PORT:I_ADDRTAG CONNECTOR:ilmb_M_ADDRTAG -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 194 - floating connection!
WARNING:MDT - PORT:D_ADDRTAG CONNECTOR:dlmb_M_ADDRTAG -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 235 - floating connection!
WARNING:MDT - PORT:FSL0_S_CLK CONNECTOR:ccx2mb_0_to_microblaze_0_FSL_S_Clk -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 332 - floating connection!
WARNING:MDT - PORT:FSL0_M_CLK CONNECTOR:microblaze_0_to_ccx2mb_0_FSL_M_Clk -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 337 - floating connection!
WARNING:MDT - PORT:bscan_tdi CONNECTOR:bscan_tdi -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_b\data\mdm_v2_1_0.mpd line 190 - floating connection!
Constructing platform-level connectivity ...
ERROR:MDT - IPNAME:mpmc INSTANCE:DDR2_SDRAM PORT:MPMC_Clk0_DIV2 -
C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v4_00_a\data\mpmc_v2_1
_0.mpd line 2158 - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify
a connection in the MHS.
ERROR:MDT - IPNAME:mpmc INSTANCE:DDR2_SDRAM PARAMETER:C_MEM_DQS_IO_COL -
C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v4_00_a\data\mpmc_v2_1
_0.mpd line 197 - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify
a value in the MHS.
ERROR:MDT - IPNAME:mpmc INSTANCE:DDR2_SDRAM PARAMETER:C_MEM_DQ_IO_MS -
C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v4_00_a\data\mpmc_v2_1
_0.mpd line 198 - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify
a value in the MHS.
The sourceless connector error disappeared after I made the selections:
Xilinx Platform Studio > System Assembly View tab > Ports tab > DDR2_SDRAM > MPMC_Clk0_DIV2 > Make External
For the two remaining parameter errors I can choose:
Xilinx Platform Studio > System Assembly View tab > Configure IP...
Interface tab > Memory Interface Generator (MIG) Settings tab >
PDF Datasheet button leading to documentation of the parameters
and
C_MEM_DQS_IO_COL
C_MEM_DQ_IO_MS
For the ML505 board, what do I choose as a column location of left/center/right (00/01/10) for each of 8 DQS pins?
What do I choose as a value of master/slave (1/0) for each of 64 DQ pins?
A different top level block
rxil -device=XC5VLX110 iop_fpga
results in
XST ERROR : Could not open $DV_ROOT/design/sys/iop/iop_fpga/xst/iop_fpga.flist at $DV_ROOT/tools/perlmod/rxil,1.1 line 196.
Edited by: sparcMT1 on Dec 15, 2008 9:04 PM

Hi sparcMT1,
I'm not sure what the problem is. When we read in the 9.2 project into 10.1, it updated cores with very few problems.
One thing you can try is to do only the automatic updates. For example, even though XPS says that "these changes need to be made by the user", just leave the MPMC with version 3.0. I'm looking at one of our projects, and it seems that we did just that.
formalGuy

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