Memory riser question

I have another 2GB (2 x 1GB) ready to install in my Pro when it arrives. I know that I should keep the 1GB (2 x 512) on one of the riser cards and put the additional memory on the other riser card. I’ve also seen it stated that the larger memory should be on riser card one and the smaller memory on riser card two. The question is can I pull out both riser cards, slide the one with the pair of 512MB modules into the number two position, add my new memory to the other card, and then slide that into the number one position, or do I need to pull the two 512MB sticks off the riser card its on and move it to the other card. Or more simply put can the position of the cards be swapped or do they need to be in their original positions.
Mac Pro   Mac OS X (10.4.7)  

Basically, for best performance you need to have Slots 1/2 on both Risers filled. From then, performance is best when you have RAM totals that are even (or 1GB difference) between them. So if you have 1GB RAM on Riser A you should have 1 or 2GB on Riser B.
There is NO difference between the Risers. They are both the same and should be treated as such.

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    2a97af4000 640K rw-p /dev/zero
    2a97b94000 128K rw-p /dev/zero
    2a97bb4000 128K rw-p /dev/zero
    2a97bd4000 128K rw-p /dev/zero
    2a97bf4000 128K rw-p /dev/zero
    2a97c14000 128K rw-p /dev/zero
    2a97c34000 128K rw-p /dev/zero
    2a97c54000 64K rw-p /dev/zero
    2a97c64000 64K rw-p /dev/zero
    2a97c74000 512K ---p /dev/zero
    7fbffe4000 112K rwxp [ stack ]
    mapped: 24255304K writeable/private: 8000K shared: 24119296K
    Solaris
    admin-srv403[2]/ # pmap 5467
    5467: oracleorprd26a (LOCAL=NO)
    0000000100000000 97696K r-x-- /oracle/product/10.2.0.4.4/bin/oracle
    0000000106066000 672K rwx-- /oracle/product/10.2.0.4.4/bin/oracle
    000000010610E000 1952K rwx-- [ heap ]
    0000000380000000 8388632K rwxsR [ ism shmid=0x4268 ]
    FFFFFFFF7B070000 64K rw--- [ anon ]
    FFFFFFFF7B100000 64K rw--- [ anon ]
    FFFFFFFF7B110000 64K rw--- [ anon ]
    FFFFFFFF7B120000 64K rw--- [ anon ]
    FFFFFFFF7B130000 64K rw--- [ anon ]
    FFFFFFFF7B140000 64K rw--- [ anon ]
    FFFFFFFF7B150000 64K rw--- [ anon ]
    FFFFFFFF7B160000 64K rw--- [ anon ]
    FFFFFFFF7B170000 64K rw--- [ anon ]
    FFFFFFFF7B19E000 8K rwxs- [ anon ]
    FFFFFFFF7B200000 8K rwx-- [ anon ]
    FFFFFFFF7B300000 8K r-x-- /usr/lib/sparcv9/libmd5.so.1
    FFFFFFFF7B402000 8K rwx-- /usr/lib/sparcv9/libmd5.so.1
    FFFFFFFF7B500000 8K rwx-- [ anon ]
    FFFFFFFF7B600000 16K r-x-- /usr/lib/sparcv9/libmp.so.2
    FFFFFFFF7B704000 8K rwx-- /usr/lib/sparcv9/libmp.so.2
    FFFFFFFF7B800000 8K rwx-- [ anon ]
    FFFFFFFF7B900000 216K r-x-- /usr/lib/sparcv9/libm.so.1
    FFFFFFFF7BA34000 16K rwx-- /usr/lib/sparcv9/libm.so.1
    FFFFFFFF7BB00000 32K r-x-- /usr/lib/sparcv9/librt.so.1
    FFFFFFFF7BC08000 8K rwx-- /usr/lib/sparcv9/librt.so.1
    FFFFFFFF7BD00000 32K r-x-- /usr/lib/sparcv9/libaio.so.1
    FFFFFFFF7BE08000 8K rwx-- /usr/lib/sparcv9/libaio.so.1
    FFFFFFFF7BE0A000 8K rwx-- /usr/lib/sparcv9/libaio.so.1
    FFFFFFFF7BF00000 728K r-x-- /usr/lib/sparcv9/libc.so.1
    FFFFFFFF7C0B6000 56K rwx-- /usr/lib/sparcv9/libc.so.1
    FFFFFFFF7C0C4000 8K rwx-- /usr/lib/sparcv9/libc.so.1
    FFFFFFFF7C100000 8K rwx-- [ anon ]
    FFFFFFFF7C200000 8K r-x-- /usr/lib/sparcv9/libsched.so.1
    FFFFFFFF7C302000 8K rwx-- /usr/lib/sparcv9/libsched.so.1
    FFFFFFFF7C400000 8K rwx-- /usr/lib/sparcv9/libdl.so.1
    FFFFFFFF7C500000 32K r-x-- /usr/lib/sparcv9/libgen.so.1
    FFFFFFFF7C608000 8K rwx-- /usr/lib/sparcv9/libgen.so.1
    FFFFFFFF7C700000 48K r-x-- /usr/lib/sparcv9/libsocket.so.1
    FFFFFFFF7C80C000 16K rwx-- /usr/lib/sparcv9/libsocket.so.1
    FFFFFFFF7C900000 672K r-x-- /usr/lib/sparcv9/libnsl.so.1
    FFFFFFFF7CAA8000 56K rwx-- /usr/lib/sparcv9/libnsl.so.1
    FFFFFFFF7CAB6000 40K rwx-- /usr/lib/sparcv9/libnsl.so.1
    FFFFFFFF7CB00000 8K rwx-- [ anon ]
    FFFFFFFF7CC00000 8K r-x-- /usr/lib/sparcv9/libkstat.so.1
    FFFFFFFF7CD02000 8K rwx-- /usr/lib/sparcv9/libkstat.so.1
    FFFFFFFF7CE00000 2184K r-x-- /oracle/product/10.2.0.4.4/lib/libnnz10.so
    FFFFFFFF7D120000 240K rwx-- /oracle/product/10.2.0.4.4/lib/libnnz10.so
    FFFFFFFF7D15C000 8K rwx-- /oracle/product/10.2.0.4.4/lib/libnnz10.so
    FFFFFFFF7D200000 72K r-x-- /oracle/product/10.2.0.4.4/lib/libdbcfg10.so
    FFFFFFFF7D310000 8K rwx-- /oracle/product/10.2.0.4.4/lib/libdbcfg10.so
    FFFFFFFF7D400000 1072K r-x-- /oracle/product/10.2.0.4.4/lib/libclsra10.so
    FFFFFFFF7D60A000 56K rwx-- /oracle/product/10.2.0.4.4/lib/libclsra10.so
    FFFFFFFF7D618000 8K rwx-- /oracle/product/10.2.0.4.4/lib/libclsra10.so
    FFFFFFFF7D700000 8K rwx-- [ anon ]
    FFFFFFFF7D800000 9272K r-x-- /oracle/product/10.2.0.4.4/lib/libjox10.so
    FFFFFFFF7E20C000 560K rwx-- /oracle/product/10.2.0.4.4/lib/libjox10.so
    FFFFFFFF7E300000 1072K r-x-- /oracle/product/10.2.0.4.4/lib/libocrutl10.so
    FFFFFFFF7E50A000 56K rwx-- /oracle/product/10.2.0.4.4/lib/libocrutl10.so
    FFFFFFFF7E518000 8K rwx-- /oracle/product/10.2.0.4.4/lib/libocrutl10.so
    FFFFFFFF7E600000 1376K r-x-- /oracle/product/10.2.0.4.4/lib/libocrb10.so
    FFFFFFFF7E856000 64K rwx-- /oracle/product/10.2.0.4.4/lib/libocrb10.so
    FFFFFFFF7E866000 8K rwx-- /oracle/product/10.2.0.4.4/lib/libocrb10.so
    FFFFFFFF7E900000 1536K r-x-- /oracle/product/10.2.0.4.4/lib/libocr10.so
    FFFFFFFF7EB7E000 64K rwx-- /oracle/product/10.2.0.4.4/lib/libocr10.so
    FFFFFFFF7EB8E000 8K rwx-- /oracle/product/10.2.0.4.4/lib/libocr10.so
    FFFFFFFF7EC00000 8K rwx-- [ anon ]
    FFFFFFFF7ED00000 8K r-x-- /oracle/product/10.2.0.4.4/lib/libskgxn2.so
    FFFFFFFF7EE00000 8K rwx-- /oracle/product/10.2.0.4.4/lib/libskgxn2.so
    FFFFFFFF7EF00000 1752K r-x-- /oracle/product/10.2.0.4.4/lib/libhasgen10.so
    FFFFFFFF7F1B4000 72K rwx-- /oracle/product/10.2.0.4.4/lib/libhasgen10.so
    FFFFFFFF7F1C6000 16K rwx-- /oracle/product/10.2.0.4.4/lib/libhasgen10.so
    FFFFFFFF7F200000 144K r-x-- /oracle/product/10.2.0.4.4/lib/libskgxp10.so
    FFFFFFFF7F322000 16K rwx-- /oracle/product/10.2.0.4.4/lib/libskgxp10.so
    FFFFFFFF7F400000 8K r-x-- /usr/platform/sun4u-us3/lib/sparcv9/libc_psr.so.1
    FFFFFFFF7F500000 8K rwx-- [ anon ]
    FFFFFFFF7F600000 184K r-x-- /usr/lib/sparcv9/ld.so.1
    FFFFFFFF7F72E000 16K rwx-- /usr/lib/sparcv9/ld.so.1
    FFFFFFFF7FFDC000 144K rw--- [ stack ]
    total 8511704K

    834881 wrote:
    I have a 4 node RAC cluster running Linux RHEL3. I know .. would love to upgrade it .. but that will take time. Looking for at survival at this point. The system is experiencing High I/O wait. How/why do you relate this to a memory problem that needs memory utilisation analysed?
    It could be that you have a dual fibre via HBA to the SAN and that one port is faulty (e.g. bad cable), thus reducing your I/O to the SAN to a single I/O path.
    It could be caused by hotspots on a LUN - and likely because ASM is not being used, this hotspot cannot be automatically load balanced.
    Or it could be a number of other factors, such as poorly designed and written app code that performs multiple passes through the same data sets, abuse of PQ slaves, etc.
    How does your storage layer look? What do you use for SAN connectivity? What diver s/w is used? How are the LUNs used (cooked/raw)? Is ASM used? What does Oracle session and instance reports ito I/O wait times? Which datafiles are being hit the hardest? Is acrhive logging used and what is the frequency of log switches? Etc. etc.
    Memory utilisation does not impact I/O, unless it is swap I/O. And these symptoms are easily seen and easily diagnosed. So I would expect that high memory utilisation may be a symptom, as is I/O wait times, of a potential underlying problem. But it would be premature to blame one (e.g. I/O wait times) on the other (e.g. memory utilisation).

  • Memory Management Questions

    Hello All!
    I read the Memory Management Programming Guide for Cocoa - several times. But some things are still not really clear.. I would like and need to have a deeper understanding. So, I hope someone could help me The problem is that I had to get rid of several (..) memory leaks in my app, and now I am a bit confused and unsure about my skills at all..
    1.
    What is the difference between sayHello1,sayHello2,getHello1,getHello2,getHello3 and which one is "better" (and why) - please dont try to interprete the logic/sense of the methods itself
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    - (NSString *) sayHello2{
    return [[[NSString alloc] initWithString:@"Hello"] retain];
    - (void) getHello1{
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    [hello release];
    - (void) getHello2{
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    [hello release];
    - (void) getHello3:(NSString *)hello{
    [hello retain];
    NSLog(@"%@", hello);
    [hello release];
    Concerning this, there are several questions:
    2.
    If I have to release everything I retain/alloc, why then do I have a memory leak, if am returning an object (which was allocated with alloc and init) from a method without autorelease. The object is still in memory. But the following method wont work. What I accept. But the object is, if returned, not reachable, but also not released. Why then is it not automatically released? (i dont mean autorelease)
    - (NSString *) sayHello1{
    return [[NSString alloc] initWithString:@"Hello"]];
    - (void) getHello{
    NSString *hello = [self sayHello1]; //wont work. the object is not there, but also not released. WHERE is it?
    [hello release];
    3.
    When is a delegate method released, if I have no variable I can use to "release"? So, if I have nothing to access the delegate like a NSURLConnection delegate?
    should I, for example, call a [self release]?
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    A Leak is only a leak if the reference to the object is lost.
    https://devforums.apple.com/message/189661#189661

  • Solaris Memory Allocation Questions

    Hi,
    I am a Columbia University engineering graduate student doing research on Solaris 10 Operating System. I just have 3 quick questions that I was unable to find answers for on the Sun Documentation website. If any1 can help me answer these questions or point me to resources that do I would really appreciate it. The questions are as follows.
    1. Does Solaris 10 provide developers with methods to ask for memory that only programs running with a certain security key or privilege can access?
    2. Also, can develops ask for private memory? I understand that during write on shared memories, copy-on-write will generate a copy of the shared memory page and make that private to the process but I am not sure if there are ways to allocate private memory at the beginning.
    3. Does Solaris 10 provide developers with methods to ask for memory that is fixed in memory and not pageable? I understand that by asking for ISM then the pages are locked in memory. But I was wondering if there are methods that an application can call that does this without having to share memory.
    Thanks,
    Larry Chen

    larrychen wrote:
    1. Does Solaris 10 provide developers with methods to ask for memory that only programs running with a certain security key or privilege can access? Solaris 10 changed everything to be based on process privileges (see the output of "ppriv -vp" for a list). It's not clear to me on a brief inspection which limits access to a processes address space but that is the mechanism.
    2. Also, can develops ask for private memory? I understand that during write on shared memories, copy-on-write will generate a copy of the shared memory page and make that private to the process but I am not sure if there are ways to allocate private memory at the beginning.Anytime you allocate heap space (eg. a call to "malloc") you get private memory. Well, technically you get it as soon as you reference it -- the call to malloc just generates the mappings, the page fault when you access it instantiates the page in RAM.
    3. Does Solaris 10 provide developers with methods to ask for memory that is fixed in memory and not pageable? I understand that by asking for ISM then the pages are locked in memory. But I was wondering if there are methods that an application can call that does this without having to share memory.Yes. First you must have the process privilege of "proc_lock_memory". After that you can call "mlock"

  • Importance of Memory Pairing Questions.

    I recently bought a 2.2ghz macbook, and left it with the 1gb of memory to keep cost to a minimum. I knew I was going to upgrade later down the line, but for much cheaper then what apple wanted to charge me. So, here I am looking at my choices. I know i want to in the end, end up with 4gb of memory, so what I am asking is what is my best choice when trying to save money.
    A: Just buy a 2gb kit (2x1gb) and wait until 4gb kits are cheaper.
    B: Buy a 2gb stick, and wait until another 2gb stick is cheaper.
    C: Buy 2gb sticks that aren't too much money (not a kit)
    D: Just get a 4gb kit.
    My real question is what's the difference if any, between a 4gb kit, and 2; 2gb sticks (sold separetly)
    thanks.

    raertadte wrote:
    I recently bought a 2.2ghz macbook, and left it with the 1gb of memory to keep cost to a minimum. I knew I was going to upgrade later down the line, but for much cheaper then what apple wanted to charge me. So, here I am looking at my choices. I know i want to in the end, end up with 4gb of memory, so what I am asking is what is my best choice when trying to save money.
    A: Just buy a 2gb kit (2x1gb) and wait until 4gb kits are cheaper.
    B: Buy a 2gb stick, and wait until another 2gb stick is cheaper.
    C: Buy 2gb sticks that aren't too much money (not a kit)
    D: Just get a 4gb kit.
    My real question is what's the difference if any, between a 4gb kit, and 2; 2gb sticks (sold separetly)
    Getting build-to-order memory isn't anywhere near cost effective, so you were probably better of not doing it. The correct memory kits for the MacBook are anywhere from under $50 for 2GB to under $100 for 4GB. Most people can capably do it themselves with a $4 #00 Philips screwdriver.
    There theoretically shouldn't be any real difference with two single 2GB should you buy them at the same time and they come from the same lot. However - you always run the chance that each module may be slightly different even if you buy them at the same time. Some brands use different memory suppliers and can change the individual ICs and/or module design. Sometimes there's different revision information. Nobody I know of has found a surefire way to ensure that the memory controller recognizes the memory as a matched pair (to achieve dual channel) short of buying a pair that is guaranteed to be identical.
    The alleged benefit of a "matched pair" or "dual channel" memory kits is that they are guaranteed to be the same, down to the exact same information in the serial presence detect EEPROM on the modules. Another benefit is that they are typically warrantied together. If one module fails, the seller will likely replace the entire pair with another matched set. The replacements that are available might not be exactly the same as the original.
    Dual channel would mean that both pairs are accessed in parallel, and should theoretically mean higher performance. I don't think it's really the bottleneck, but apparently it results in slightly higher video performance with the integrated video that uses a segment of the system memory.

  • Update on Memory, plus Question

    I have decided to go for 2 x 256mb 400mhz DDR DIMMs, plus 1x 512mb DDR 400mhz.
    After reading all of the posts here, I am now more confused than ever.
    I'm going to place my order for them on Feb 1st.
    What I would like Tiresmoke, or anyone else to  do is to answer two questions.
    Firstly, will this combo work??
    Secondly, where to put the new sticks(ie which Dimms).
    Finally, the Bios matter...just how is that done??????
    If this matter could be answered as soon as possible, I would be really grateful.

    The advise already given Memory Upgrade. seems sound.
    Quote
    2 x 256mb 400mhz DDR DIMMs, plus 1x 512mb DDR 400mhz
    is not a good configuration for your mobo
    See Main Memory
    Quote
    Firstly, will this combo work??
    - Doubt it
    Quote
    Finally, the Bios matter...just how is that done??????  
    - See manual - Cell Menu P58 or Section 3-23
    In the Dram configuration The Memory Timings Auto settings  are read from the spd chip on the memory module. These are the manf recomended settings but sometimes need to be set manually:-
    1)Like some corsair brands which need different settings to run on the AMD64
    2) Where modules with different timings are used.

  • Memory Timinigs Question?

    I have two sticks of 512 Corsair.  One is LL and the other is XLL.  I have the volts at 2.7 and they are in slots 1&2.  If I leave the timings on auto I get random Blue Screens of Death.  If i raise them to 2.5-3-11-3 everything seems stable (I ran Prime 95 over night and 3Dmark 01 at the same time.  Memtest tonghit).
    So my questions is:
    1. Is this normal?
    2.  I'm at T2 right now.  Is T1 generally more unstable?
    3.  When I run MemTest, how long do I run it for?
    4.  Anything else I should try?  I've heard that placing the memory in slots 1&3 is better.  is this true?

    As youve got 2 different models the timings on the spd (the control chip on each module) will i suspect have different timings. The spd settings are used when selection is set on auto. Therefore you get glitches.
    by overiding auto with 2.5-3-11-3  you have selected a timing that both modules can run at.  
    if you want to compare modules try each module on auto & view settings using Everest or CPUID, logically both should run at the speed of the slowest module.
    It's a nice exercise youv'e done & dispels the theory some have that these mobos need matched pairs.

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