Multi-Chassis Power Up Time Delay - DIP switch on PS Shuttle?

We run into this problem with multi-chassis setups. The downstream PXI chassis have to be powered up first before the controller one.
How do you solve this in a world-voltage capable way? I know there are power-sequencing power strips for North America, but this is an added expense, and not world-voltage capable.
Would NI consider a time-delay DIP switch on the back of the PXI power supply shuttle? That could reliably provide controlled power up sequences and be world-voltage capable (90-250 VAC 50-60 Hz)

Craig,
Thanks for posting your suggestion. Unfortunately, we do not yet have such functionality on our equipment. However, I would encourage you to post this suggestion on our idea page. www.ni.com/ideas
Customer Education Product Marketing Manager
National Instruments

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How to read USER1 DIP-switch status of a cRIO chassis from FPGA?

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Solved!
Go to Solution.

Hi, this is the correct information. You cannot read from the FPGA the DIP switch status. The only thing you could do is to use the Read Switch.vi function located under Functions -> Real Time -> RT utilities palette
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I have seen that kind of issues here and there is something you can try in order to correct this problem:
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Hope this helps!
David

DAQ AO to AI time delay

Hallo,
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Hi IoInNBlack,
first of all thank you for posting in this forum.
I think you should synchronize your input/output operation, otherwise I don´t understand how you can take the timestamps and consider them
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Message Edited by pxchellone on 07-06-2009 09:23 AM
Attachments:
Multi-Function-Synch AI-AO.vi ‏35 KB

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Last edited by Aton (2013-04-12 12:14:19)

Okay, I have found the problem.
Seems that I hadn't correctly enabled [email protected].
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Hello All,
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Hi
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Attachments:
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Sorry to refresh such an old topic - but I am stuck with exactly this: Monitoring power supplies of a stacked Cisco Catalyst 3750-E.
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snmpwalk -v 2c -c public 192.168.1.50 1.3.6.1.4.1.9.9.13.1
SNMPv2-SMI::enterprises.9.9.13.1.1.0 = INTEGER: 13
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SNMPv2-SMI::enterprises.9.9.13.1.3.1.2.2006 = STRING: "SW#2, Sensor#1, GREEN "
SNMPv2-SMI::enterprises.9.9.13.1.3.1.3.1006 = Gauge32: 41
SNMPv2-SMI::enterprises.9.9.13.1.3.1.3.2006 = Gauge32: 40
SNMPv2-SMI::enterprises.9.9.13.1.3.1.4.1006 = INTEGER: 59
SNMPv2-SMI::enterprises.9.9.13.1.3.1.4.2006 = INTEGER: 59
SNMPv2-SMI::enterprises.9.9.13.1.3.1.5.1006 = INTEGER: 0
SNMPv2-SMI::enterprises.9.9.13.1.3.1.5.2006 = INTEGER: 0
SNMPv2-SMI::enterprises.9.9.13.1.3.1.6.1006 = INTEGER: 1
SNMPv2-SMI::enterprises.9.9.13.1.3.1.6.2006 = INTEGER: 1
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SNMPv2-SMI::enterprises.9.9.13.1.4.1.2.2059 = STRING: "Switch#2, Fan#1"
SNMPv2-SMI::enterprises.9.9.13.1.4.1.3.1060 = INTEGER: 1
SNMPv2-SMI::enterprises.9.9.13.1.4.1.3.2059 = INTEGER: 1
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SNMPv2-SMI::enterprises.9.9.13.1.5.1.2.2060 = STRING: "Sw2, PS1 Normal, RPS NotExist"
SNMPv2-SMI::enterprises.9.9.13.1.5.1.3.1059 = INTEGER: 1
SNMPv2-SMI::enterprises.9.9.13.1.5.1.3.2060 = INTEGER: 1
SNMPv2-SMI::enterprises.9.9.13.1.5.1.4.1059 = INTEGER: 2
SNMPv2-SMI::enterprises.9.9.13.1.5.1.4.2060 = INTEGER: 2
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Model WS-C3750E-48TD
Firmware 12.2(37)SE1
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PXI Chassis Power LED Flashing Red: What to do?

My NI PXI-1042 keeps blinking red the Power LED. I know it means the voltage is out of the specs. What to do?

FilipeTaveiros wrote:
But it is not continuously red.. It is blinking red.. Thanks for your help. Anyone?
This is copied right out of the manual:
The chassis power switch has an integrated LED. This LED indicates one
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Oct 30 11:42:09 mashugana kernel[0]: Kext com.apple.iokit.AppleYukon2 not found for unload request.
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BTW: what does
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Attachments:
flow vis + trigger-m.vi ‏939 KB
flow vis + trigger-m_2.vi ‏895 KB

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Multi-Chassis Power Up Time Delay - DIP switch on PS Shuttle?

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