Network graphic for Development Plan
how can I access Graphic Network for creating Development Plans through transaction OOEC. When I click on the network graphic icon, it takes me to SAP standard screen not to the graphic editor. I face the same problem with transaction PPDPIM.
However, it works properly for creating career path (transaction OOQ4)
kindly help me on this as i need it urgently.
Best Regards
Even I'm facing the same problem.
Waiting for Reply
Similar Messages
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Iview/ Page for Development plan
Hi,
I want to display/ maintain the Individual development plans in ESS. In backend its maintained using transaction PPDPIM.
Does there exist any default page/Iview that i can use for this or I have to define a transactional oview.
Please advice.
Thank You!Hi,
I searched for the PDP in ESS, but I can't find any.... As you are telling that you already have a T-CODE for the same go for SAP T-CODE iView.
Regards,
SrinivaS -
Development Plan Configuration details for Talent Management
Hi Gurus,
I need to know the configuration nodes used for Development Plans in Talent management.I created the development form in Talent Assessment -->Define Forms for Talent Assessment. & assigned a scale to it.
Now when I log in with the TMS id in portal & create a development form for one of the employees, I can see certain links & fields like : Add Action (link), when i click on Add action a screen pops up & asks for Action Type & Action Status.
Firstly i need to know where does these values get fetched from.
Secondly when i click on Add Action button, ideally it should give me 2 options :1. Add actions that can be freely defined and 2. Add training,but currently it just opens a window to create a new action.So how to control the same.
Regards
BhartiHi,
I know this is a (very) old post but my answer might help someone anyway.
1. Actually, the dropw-down lists are filled from the table T77TMC_SCA_MAP, status is mapped with scale 8 and type is mapped is scale 9.
Customizing of this table can be reached trough transaction S_EH4_55000247.
2. The option is only shown when LSO integration is active.
Hope it helps.
Best regards,
Guillaume -
Need help Development Planning : Part of Talent Management
Hi All,
I need to turn on new functionality for Development Planning (part of Talent Management), I looked online for material..I did find some but none of them explains configuration steps.
Can someone guide me on the same.
Regards,
Shwetahi
can u explain what exactly are you trying to do ,?
which enhancement pack you currently are on?
Regards
sameer -
Goodday Boffins!
We have implemented Portal for ESS and MSS. In a number of cases, we have experienced problems where a manager who has a manager, cannot access certain items, especially IDP items for development planning. I would appreciate any feedback from whoever has experienced an issue like this or if anyone is well versed in PD profiles and portal access.
Regards
JulianMoved to ESS Forum...
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Hi All,
Can anyone throw light on how to change the legend in the network graphic for PS? For exmaple, is there a way to display partially confirmed activities in Yellow vs finally confirmed activities in Red?HI,
Never tried but the config layout seems as if it is possible.
Follow the config path :
"sap netweaver - application server - front end services - network / hierarchy - define graphics profiles / node / links / colors etc.."
Standard graphics profile would be "PS - Network". Go to the "Node Group" list in that. (multiple selection icon).
try to find "PS_N_______1" group. Under this group you find number of color codes & form lines for each of the project objects (with their state).
Select activity part conf / fully conf & enter your required color there.
Pls share your experience on this, if you explore the above way.
regards -
Add support for products that say No development planned in Vi
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Macmini among the latest i5 or i7 are they appropriate for web/graphics/software development?
Can operate with ease with Adobe Creative Cloud cs6 Apps? Also with xcode or Eclipse etc IDEs?
Also can get carried easily, and is 240/110V voltage Europe/USA?
MACmini server have all abilities of macmini client plus more, hence, can run Adobe Creative Cloud cs6 Apps, xcode & Eclipse?Electrical and Operating Requirements
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Frequency: 50Hz to 60Hz, single phase
http://store.apple.com/us/browse/home/shop_mac/family/mac_mini/select
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http://news.softpedia.com/news/What-You-ll-Need-to-Run-Adobe-CS6-Mac-System-Requ irements-267982.shtml
http://prodesigntools.com/products/adobe-cs6-system-requirements.html -
I got an iphone from three network Uk, I am planning go to have holidays abroad for one and a half month, I request to my mobile company if they can unlock my iphone to use abroad with another sim , after one week they unlock my mobile.and my basic questions , if for any reason someone stole my iphone, they can activate in other country because my iphone is unlocked with the original codes.
Yes.
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Table for maintenance plan and maintenance cycle and Unit
Hello,
I need to know the table where the values are stored for maintenance plan, maintenance cycle and Unit.
I know that we can get the maintenance cycle and unit from MMPT table.
Question 1
If the maintenance plan has only a single cycle then the data is stored in above table MMPT, but if a maintenance plan has mutiple cycles like 1 maintenance plan has maintenance cycle as 364 Days and 1092 days then the data is not stored in MMPt table.
Question 2
Requirement is I need to develop a report where in I need maintenance order, maintenance plan and the relevant maintenance cycle and unit. Supose an maintenance order is created for the above maintenance plan which has 2 maintenance cycle how can I identify for which maintenance cycle the order is created.
Regards,
NarendraHi,
Please review PM tables
PM/SM/SD Tables
MPOS Maintenance Items
AFAB Network - Relationships
PLKO Task list
PLAS
AFFH Operations
PRT assignment data for the work order
AFFL Work order sequence
AFFT Order process instructions
AFFV Order process instruction values
AFFW Goods movements with errors from confirmations
AFIH Maintenance order header
AFKO Order header data PP orders
AFPO Order item
AFRC Table of planned changes to conf.: Automatic goods receipt
AFRD Default values for collective confirmation
AFRH Header information for confirmation pool
AFRU Order completion confirmations
AFRV Pool of confirmations
AFVC Operation within an order
AFVU DB structure of the user fields of the operation
AFVV DB structure of the quantities/dates/values in the operation
MPOS Maintenance ITEM
AFWI Subsequently posted goods movements for confirmations
AUFK Order master data
AUFM Goods movement for order
MPLA Maintenance Plans
BGMK Master warranty header
BGMP Master warranty item
BGMS Text item master warranty
BGMT Master warranty text
BGMZ Warranty counter information
CRHD Work Center Header
CRTX Text for the Work Center or Production Resource/Tool
EQKT Equipment short texts
EQST Equipment link to BOM
EQUI Equipment master data
EQUZ Equipment time segment
HIKO Order master data history
IFLO Functional Location (View)
IFLOT Functional location (TABLE)
IFLOTX Functional location: Short texts
IHGNS Plant maintenance permit segment
IHPA Plant Maintenance: Partners
IHSG Object-related permits in Plant Maintenance
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Regards
Carlos -
Tool for Explain Plan??
Hi
Is there any tool avialable for explain plan that will give a graphical representation of the flow??Thanks 3360,
I agree the export or copy functionality from some of these tools leaves a bit to be desired, but the original post here was in regards to an easier tool to use for self diagnosis. Maybe this can be remedied through feedback to the product manufacturers.
I know its good to have a familiarity with the lowest common denominator when it comes to database interfaces, and its also good to have an appreciation of what's going on behind the scenes when you press a button. But for productivity's sake, I left vi/notepad and sqlplus behind long ago as my main development/management environments.
Regards
Andre -
Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?
Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1- Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
· The Code size and speed optimization.
· Developing time.
· Compiling time.
· Verifying time.
· Ability to developing in future.
· …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3- I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4- I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
Go to Solution.Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy. If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores -
Error while creating a Development plan template
Hi Gurus,
I am facing errors while creating Development Plan Template.
This is how it goes :
When i click on Define Forms for Talent Assessment --> a wizard pops up & i select Development Plan :
In first step, I am giving Title,Integration with SAP Learning Solution (check) & a rating scale.
Now after clicking next, I am adding 2 development areas :
1) Training
2) Mentoring,
now as soon as I'm clicking on End Configuration, It displays 2 errors & 1 warning message :
error1 : Element Appraisal Template 'XXXXX' contains errors.Cannot change status.
error2 : Value type 000000XXX of value class Q does not exists
Warning 1 : You have maintained a description that is not displayed.
In PHAP_CATALOG, when I'm trying to manually release the Criterion Group (VB) or Appraisal template (VA), it does not allow me to do it.
Kindly let me know how to proceed further.
Regards
bhartiHi,
Even though it gives the error,the new RTF template is uploaded and it is reflected when I query the template again.
But when I run the Concurent program and see the output,the output still shows me the old template.
Regards
Jujaar -
Can i use subfolders with source control for developer ?
We'd like to use the repository as source control for our developer files.
We planned to use the following structure in the repository:
- Application Container
- Folder
- Files
We uploaded the files in the repository.
Now if we open the file through the ron the file will open in form builder, which is pretty good.
The following thing I'de like to do is a checkout of the file ... ok ...i'm going to file - administration - checkout - the message occurs: no versionable object exists ! ... ? :-(.
So I go to file - administration - source control options .. i'd like to say forms that it has to look for the file in a subfolder of the application system .. ok.
After changing this i try again - the same message.
If I return to source control options the container entry has been changed to the application folder.
Are Subfolders not supported by the source control for developer ?
Does anybody have the same effects ?
Background informations ?
Thanks in advance
Mario
null<BLOCKQUOTE><font size="1" face="Verdana, Arial, Helvetica">quote:</font><HR>Originally posted by [email protected]:
Did you check the file in first? When you first put files in Repository, they are initially unversioned until the first checkin...
Brian<HR></BLOCKQUOTE>
Hello Brian
Sorry, for the delay. I worked for some day for another customer.
Yes, i did.
I'm working like this:
- upload file with check in Folder which is under an application Folder (app - fmb )
- then i check out the fmb in the repository
- doubleclick in repository, which opens the form in form builder
- change the file
- File - Administration - check-in - connect to repository - choosing the workarea - and defining the folder (app - fmb ).
- The file will be check-in, but directly under the folder app.
Thanks in advance
Mario
null -
Can FW CS3 be used for graphic for printing?
I am very familiar with FW but I do not like Photoshop,
however I have both I preffer to use FW. As I have seen on one
presentation new FW CS3 has CMYK pallete so my question is: can FW
CS3 be used for preparation of graphic for printing or what are the
obstacles? After preparing images in FW I will use InDesign for
text or maybe the text in FW is wector and maybe I could use FW
including text and not to use INDEsign far small projects? Does
anyone has any experience with this subject?
Regards
Martinqnnick wrote:
> I am very familiar with FW but I do not like Photoshop,
however I have both I
> preffer to use FW. As I have seen on one presentation
new FW CS3 has CMYK
> pallete so my question is: can FW CS3 be used for
preparation of graphic for
> printing or what are the obstacles?
Fireworks does not operate or export in CMYK color space. It
was
developed for screen images only, and operates and exports in
RGB color
space. It is not recommended that you use it in preparation
of images
for print. You mentioned that you don't like photoshop. You
might like
Illustrator better.
Linda Rathgeber [PVII] *Adobe Community Expert-Fireworks*
http://www.projectseven.com
Fireworks Newsgroup:
news://forums.projectseven.com/fireworks/
CSS Newsgroup: news://forums.projectseven.com/css/
http://www.adobe.com/communities/experts/
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