NVIDEA outputs digital signal to LCD projector

We are having a different problem with connecting to LCD projectors at our school. The problem seems to result from a Crestron media manager between the MBP and the projector. the MBP connects via the DVI-to-VGA adaptor. If the MBP has the NVIDIA GeForce 8600M GT card, it sends a digital signal to the projector and nothing shows up on the screen. Displays preference panel shows the 2nd monitor as "Digital 170T." There are 3 MBPs showing this behavior. one older MBP with an ATI Radeon X1600 card connects just fine. My G4 with an ATI Mobility Radeon 9700 also worked (for over 3 years). both show a "VGA" connection in Displays preference panel.
The NVIDIA MBPs can connect directly to an LCD projector and output a VGA signal that works. it seems that the intermediate Crestron system is not sending a signal that the NVIDIA requires to know it is connected to a VGA display. and of course, Crestron is telling our support people it is not their problem; NVIDEA's web support doesn't even touch Mac topics.
So how do we convince the NVIDIA card to output a VGA signal from the DVI port?

Nvidia Control Panel. Change the video output. Should work.

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Attachments:
SolenoidValve1.vi ‏24 KB

Hey friends,
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How to input/output a digital signal and acquire an analog signal at the same time?

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Acquirement Card: PCI1002L
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Hi,
Have things changed over the years?
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Counter Output as Sample Clock of Digital Signals

I have a situation where I need to use a hardware counter as sample clock of digital output signals.
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/pek

Thank you for your answers, but I can't get it to work.
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Sequence 1create output digtal signal- 2 make microseconds delay or less- 3 measure digital signal with board 6023e

hello
I need creat a digital signal and for this i use a counter output and then i need creat a delay after a signal measurment and for this i use again a couter. My problem is how i can make this delay betwen create and measure a signal. this delay must to bethe shortest possible and precise. une of my attemps was make a sequence and for make the delay i create a task for une virtual output with max frequency 5000000hz and just une pulse but i dont know how many time the labview get to go by the first task ( creat a output pulse and ent it) to make tis task before discribed to the last task (measure a digital sinal). Another thing that i dont know is how many time the libview get to create and eliminate une task. Une information beyond the kind of board (6023E) that can be useful to help me with this problem is the information about my pc in this case i use a pentium4 3Ghz.
thanks

...My problem is how i can make this delay betwen create and measure a signal.
...how many time the labview get to end one task and start another one.
What I tried to say is, that even if you use the counter of the 6023e-Board
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How to output a digital signal on negative slope of the clock?

Hi
I need to output a finite length of the digital pulse which will start on demand at the negative slope of the imported (or exported) clock.
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Pawel
Solved!
Go to Solution.

Which device are you using to generate your digital signal. What is the clock source? Can you attach your vi? Normally, there is a DAQ function to configure the trigger where you choose the trigger source and the trigger slope (rising or falling), which would be falling for a negative slope.
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Inventor of the WORM Global

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FPGA Digital Signal Output Problem

Hi,
I am having a problem outputting a signal through my PCI-7831 and would appreciate any advice anyone has as I am beginning to crack the wall where I am banging my head into it.
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The FPGA VI consists of 3 while loops though only 2 loops are not performing as expected. The FPGA while loops in question contain a single sequence structure that has as their first frames an IRQ 0 and 1 respectively .
In the host VI I am waiting for IRQ, writing the value of 2 wait timers, and acknowledging the IRQ in the first frame of a sequence. The FPGA then sets the states of 2 DIO outputs to both high. Then the timers keep both outputs high until the next frame is reached, then 1,0 is written, the second wait expires, and the loop repeats until the while loop conditions in the host VI are met and the sequence in the host VI indexes (this is about 1 second.)
For the second loop, I am going to the next frame in the host VI. This host works the same as the above sequence but only 1 value is being written, 0,1.
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The last, and only the last, iteration of the "both high" period is wrong. The 1,1 becomes 1,1, then 0,1 about halfway through the wait, then the 1,0 occurs properly, then the 0,1 period begins properly.
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I am using these signals to control a custom high amplitude bipolar digital signal generator.
I have posted my VI's if anyone would like to see them.
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Message Edited by bugsmashers on 07-21-2005 12:57 PM
Message Edited by bugsmashers on 07-21-2005 12:58 PM
Attachments:
Preset_power_top_WHILE_loops1.vi ‏311 KB
Digital Pulse Amplitude Control Preset Power.vi ‏216 KB
preset_power_data_gen_FPGA.vi ‏684 KB

Hi Ben-
I took a look at your code, and I can explain the first error you are talking about, but I don't think I understand the second error. For the first error, lets start on the last iteration of the first while loop in your host code. It first waits on IRQ 0, then sets the 'high' and 'low' parameters on RT, then acknowledges IRQ 0. At this point on the FPGA side, the top loop (1,1 loop) begins to execute and sets the lines to 1,1. Meanwhile back on the host, your first loop completes and the second loop starts. The first thing the second loop does is wait on IRQ 1. It doesn't have to wait at all because IRQ 1 was set long ago when the FPGA program started, so it clears IRQ 1, and the second FPGA Loop immediately sets the lines to 0,1. The next thing that happens is your top loop in FPGA (1,1 loop) finishes waiting for the time specified in 'high' and moves to the next sequence frame and sets the lines to 1,0, next the second loop finishes its wait ('Wait Zero') starts the loop over again, sends IRQ 1, which is handled by your second host loop, it acknowledges IRQ 1, and then your second FPGA loop sets the lines back to 0,1. Long explanation, but I hope not too confusing. Synchronizing the host and FPGA with everything happening in parallel can get to be a lot to wrap your brain around.
One comment on the code - From your description and looking at the code it looks like the first pulse iterates for a given period of time, then the second. The way you have it written right now the pulse period will not be very deterministic - especially if you are using windows as your host. The reason is that every iteration of the pulse depends on an IRQ interaction, which means you are waiting on your host CPU to do something. Granted, the host should react quickly, but it is not deterministic - if windows is your host, and you start dragging windows around, you'll notice your period become longer than 'high'+'low'. A better architecture might be to send the number of iterates of the 1,1 - 1,0 loop you want to execute down to FPGA, and let FPGA count the iterations and report back when it's done. Then start the second loop, or send all the info down to FPGA and let it control both loops. If setting 'high', 'low', and 'wait zero' need to happen through out, use the read/write control to just update those on the fly from the host rather than making the FPGA halt while they are updated. If determinism on the period length is not important for your code, or you designed it the way you did for other reasons, then ignore everything I just said .
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Dustin

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When I connect the cable to my Macbook, the opened application streched out to a full screen (seems like computer detets the cable) but projector says 'no signal'.
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Thanks much
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I'm still stucked.
By reading some articles, it says even using mini DVI adapter, the signal is still digital and if the projector doesn't accept digital signal then it's no use....
My projector is Epson EX3200 and it doesn't have any DVI or HDMI input.
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Why should this world be so complecated.....

Can't connect MBP to LCD projector using DVI-TO-VGA adapter

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Sorry Walter, but according to the Terms of Use (which you agreed to the first time you logged in to the Discussions and can be found if you click on the "Help" link to the right):
Do not post a URL unless it directly answers a user's question.
The URL you post does not answer David's original question. Also, it could potentially void his warranty because a firmware hack (and this is indeed a link to a "hack") is an unauthorized alteration to the hardware of his computer. ("Software" can only be installed on the hard drive and that hack is not installed on the hard drive, it's installed on the firmware on a chip inside the logic board.)
I don't want to take this thread off-topic, but your reply does NOT help David's situation. I would, however, value your input and anyone else's to this and any other topic in the Discussions as long as it is pertinent to the original subject.
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Is there a better way to generate custom timed digital Signals

I am trying to generate digital output of high and lows with particular delays on different lines. Each daq assistant is activating single line on a port on USB 6501. There more complex high and lows that I need to generate with variable time difference between high and low. There is codebelow which accomplishes what I am trying to achieve but for executing a long pattern of high and low signal is very time consuming to do this way. I am sure there is a better way to do this, I not a expert on labview so I haven't uncovered its full potential. Can anybody suggest a more effective and a quick way to do this. I would hgihly appreciate. Thanks!
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Solved!
Go to Solution.

See the attached file
Attachments:
Digital Signal.vi ‏335 KB

NVIDEA outputs digital signal to LCD projector

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