Overclocking causes pc to restart in a loop

I have a msi z68a-g43 g3 motherboard that is brand new. Whenever I enable the genie oc feature under bios, the pc would go in an endless of restarting the pc.The pc would no remain on for more than 2 seconds when I turn it on. The only way to fix this is to reset the cmos. Under standard mode feature in bios, the pc would start up normally.
The bios version currently is 4.00.

Quote from: Bernhard on 05-February-12, 14:57:56
The specs for the PSU are normally on a lable on the side of the PSU.
Yes, the OC Genie will normally clock to 4,2GHz.
Does your system run normally in stock? 
Yes, I see no glitch running in normal mode. The only item I didn't is the asus dvd writer. That shouldn't be an issue with the power issue I would imagine.

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    This topic has been moved to Overclockers & Undervolting & Modding Corner.
    https://forum-en.msi.com/index.php?topic=156631.0

    Quote from: Bernhard on 05-February-12, 14:57:56
    The specs for the PSU are normally on a lable on the side of the PSU.
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    Quote from: GD_Fritz on 07-July-12, 11:15:22
    Also could it be my Vbios is somehow corrupted or causing this as it always seems to happen when windows is booting up before I have access to my machine right when it would be accessing the vBios?
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    Quote from: GD_Fritz on 07-July-12, 11:15:22
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    Kernel Version: Darwin 8.5.0
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    Working with LV 8.2.1 real-time to develop a host of applications that monitor or emulate computers on RS-422 busses.   The following screen shots were taken from an application that monitors a 200Hz transmission.  After a few hours, the PXI station would crash with an awesome array of angry messages...most implying something about a loss of memory.  After much hair pulling and passing of the buck, my associate was able to discover while watching the available memory on the controller that memory loss was occurring with every loop containing a VISA read and error propogation using the data nodes (see Memory Leak.jpg).  He found that if he switched the error propogation to regular old-fashioned shift registers, then the available memory was rock-solid.  (a la No Memory Leak.jpg)
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    Dan Marlow
    GDLS
    Solved!
    Go to Solution.
    Attachments:
    Memory Leak.JPG ‏136 KB
    No Memory Leak.JPG ‏137 KB

    Hi thisisnotadream,
    This problem has been reported, and you seem to be exactly reproducing the conditions required to see this problem. This was reported to R&D (# 134314) for further investigation. There are multiple possible workarounds, one of which is the one that you have already found of wiring the error directly into the loop. Other situations that result in no memory leak are:
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    2.  If the case structure is gone and just blindly check the bytes at port and read every iteration.
    3.  If the Timed Loop is turned into a While loop.
    Thanks for the feedback!
    Regards,Stephen S.
    National Instruments
    Applications Engineering

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