Passing data from RT host to FPGA through DMA FIFO

Question

Hello,
I am trying to write some data from an RT host to FPGA target using DMA FIFO then process this data and then read them back from the FPGA target to the RT host through another DMA FIFO. I am working on NI PXIe chassis 1062Q, with NI PXIe-8130 embedded RT controller and NI PXIe-7965R FPGA target.
The problem I am facing is that I want to send three different arrays, two of the same size and the third one with different size, and I need the smaller one to be sent to the FPGA first. I tried using flat sequece with two frames in the FPGA VI. In the first frame I read and write the first array in a while loop which is finite (i.e., finite number of iterations). The second frame contains the process of reading and writing the second two arrays (of the same size) in a while loop that can be finite or infinite (according to a control). The problem is that this didn't work. The 2 arrays are displayed on the front panel of the RT host VI and are working fine, however, the array that should have been read in the first sequence doesn't show up on the front panel of the RT host VI. This doesn't make sense because if it is not passed from the host to the fpga and vice versa then the second frame shouldn't have been executed. Note that I am wiring (-1) to the timeout to block the while loop iterations till the passing of each element is complete. Thus the first while loop has 3 iterations only. Could someone help me undersdtand why this happens and how to solve this problem?
I am attaching a picture of both the host and the fpga vi.
Thank you.
Solved!
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Attachments:
RT host vi.png ‏102 KB
FPGA vi.png ‏28 KB

Answer 1

No need to initalize the arrays with values that you will immediately overwrite.  Here's what I believe to be equivalent code:
The array outputs should be wired directly to the FPGA FIFO writes.  Do not use local variables when you can wire directly.
If you know that you want to transfer the Temp Data Array first, why not make your code do that?  Eliminate the sequence structure, and put the functions in the order in which you want them to execute.  Use the FPGA reference and error wires to enforce that order.  You might consider writing the Temp Data Array, reading it back, then writing the Real and Imag A arrays, to see if that gets you the results you expect.  Run the code in simulation (in the project, right-click on the FPGA target and execute on the host with simulated IO) so that you can use execution highlighting and probes to see what is happening.  Wire the error wires through and see if you get an error anywhere.  Make sure you're not missing something simple like looking at the wrong starting array index.