PCI Express v1.7 timing simulation hangs on link training

Question

Using:  ISE 14.7, PCI Express Endpoint core 1.7 (2.5GT/s, 125MHz, 4-lane, Gen1, for ML605, verilog), p/n xc6vlx240t (ff1156, -1), QuestaSim-64 10.3
Successfully did functional simulations of Xilinx supplied example_design for PL_TRAIN_FAST either 'TRUE' or 'FALSE'.  The latter takes longer as expected. The message "Transaction Link Is Up" comes at ~10.7ms for FALSE, or ~15us for TRUE. 
However, after implementation, timing simulation hangs after message "Transaction Reset Is De-asserted" which should be followed by "Transaction Link Is Up".  Tried both TRUE and FALSE for the root endpoint model (N/A for the endpoint model for timing simulation) but no difference.  Ran the sim up to ~300msec (took many hours) but still no link up.
Tried making changes per AR#42123 but no difference. 
What's wrong?
Also note, there was no timing simulation folder provided by Xilinx in this particular example_design -- why?

Answer 1

Hi,
Default testbench, example design do not support upstream transfers
Please enable BME for EP and RC and retry
Go through below AR for more details
http://www.xilinx.com/support/answers/36829.html
Hope this helps
-Vanitha