Problem in output of project in mp3 format

Hi
I recently completed the arrangement of a 2:50 mins music project. When I exported its audio mixdown in WAV format, the ouput was perfect. However, when I am exporting the output in mp3 or wma format, the length strangely increases to 5:40 mins and the tempo of the music obviously becomes extremely slow. When I tried to convert the WAV output into mp3 by a free MP3 converter, all I could get was disturbance.
Please help me out of this strange problem!

What operating system?
What version of Premiere Pro? Have you updated to Premiere Pro CS5 (5.0.2)? That update fixes a lot of problems.

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Boattt wrote:
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mimizuff wrote:
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A: problem: program outputs numbers in scientific notation

Or upgrade to JDK 5.0 and user the new java.util.Formatter capability.
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$ LC_ALL=en_NZ   java A
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cheeto22 wrote:
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Hello,
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[HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen_demo.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen_demo.vhd":1]
Analysis Results[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen.vhd":1]
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
set_property target_language Verilog [current_project]
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
sources_1[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen_demo.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen_demo.vhd":1]
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
update_compile_order -fileset sim_1
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/fsm.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/fsm.vhd":1]
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/fsm.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/fsm.vhd":1]
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[HDL 9-1654] Analyzing Verilog file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sim/testbench.v" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sim/testbench.v":1]
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/debounce.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/debounce.vhd":1]
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2013.4/data/ip'.
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[IP_Flow 19-1704] No user IP repositories specified
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
Vivado Commands[Project 1-11] Changing the constrs_type of fileset 'constrs_1' to 'XDC'.
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
sim_1[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[HDL 9-1654] Analyzing Verilog file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sim/testbench.v" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sim/testbench.v":1]
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[IP_Flow 19-234] Refreshing IP repositories
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
[IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/debounce.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/debounce.vhd":1]
[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
[HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen.vhd":1]
set_property constrs_type XDC [current_fileset -constrset]

We had the same problem when switching to Ubuntu 14.04, and there actually is a solution for it: make sure your locales are set to English.
$> env | grep LC_*
should only show english (or C) locales, all others are known to cause parsing errors in some numbers, usually caused by wrong string-to-float conversions (e.g. 18,29 in german is 18.29 in english). You can change the locales in the file /etc/default/localesThis is not the first time we had problems with the locale settings, Xilinx does not seem to test their software with anything else than en_US, causing obscure bugs like this one.
HTH
Philipp

Problem in output of project in mp3 format

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