Problems retriggering

Question

Greetings. I am using a PXI 6289 and I need to generate a fast continous pulse traing that is synced with an external clock. I have foudn several examples which at the core all have same base. Use a counter to generate a finite number of pulses that is trigered from the external clock and then retrigger it.
http://sine.ni.com/devzone/cda/epd/p/id/2415  Here is the most basic example.
So I have a 5kHz clock and I am putting it into the SRC of counter 0 (PFI8)
I use that as my trigger for CTR 0 output. I tell it to make a 50kHz clock and make 100pulses.
It does this well except when it goes to retirgger it misses one full cycle of the external clock. So the new pulse train is not continous. I have been looking through the posts and this should work. If you do 99 pulses you can see it does not miss a full cycle but the two clocks are no longer synched if you look at the signals on a scope.
In the end I jsut need to generate a fast clock from a slower clock and it needs to be continous. I would like it to work with the 6289 but I am beginning to open my mind to getting a new card if this doesn't work.
If anyone has any suggestions I would greatly appreciate it.
~D

Answer 1

Hi Glish Lab,
The reason you are missing a full cycle of the external clock is likely due to the trigger rearm time on the PXI-6289.  I have a few questions as well as suggestions that might help us find a better solution for you. 
Do you know the accuracy of the 5kHz external clock?  I ask this because this would help us determine if you might be better off using a phase-locked loop (PLL) with the PXI backplane clock.  Depending on which PXI chassis you are using, the accuracy of the backplane clock might differ but is around +/- 25 PPM for the PXI 1042.  If your external clock is less accurate than the backplane clock, you might be better off bringing it in as a reference clock so that it will be PLL'd to the higher accuracy backplane clock. 
The only problem PLLing to the backplane clock is that they are only phase locked and not synchronized.  You will have to wait a few cycles of the 5kHz external clock for the backplane clock to fully PLL.  This also means to synchronize the two you will need to provide a digital pulse as a start trigger (after these few cycles) to synchronize the backplane clock.  You would then be able to divide down the backplane clock by an integer to adjust the sample clock to whatever you would like.  Regardless of whether the accuracy of your clock is greater or less than the backplane, you can still bring in the external sample clock as a reference clock (PLL'd to the backplane) and provide a digital pulse start trigger to gain a faster synchronized clock. 
If you could provide more information about the source of the external sample clock and details of the other devices you're using in your application, it might help me find a better solution. 
I hope this helps,
Paul C.
Message Edited by Paul C. on 10-25-2007 03:22 PM