Prroblem to rest the sample in QAC3

Dear all,
I am trying to reset the sample for the Inspection lot in QaC3. But I am not able to do it. The Inspection lot status is REL, INSP.
I think if the inspection lot status is INSP,it will not allow. Is it correct?
If so, Please guide how I can deactivate the INSP status.
The background is, we tried to do the results recording in QE01, but it gave the mess "Express document update was terminated by user". We found the reason that the Sampling Procedure assigned to MIC was wrong.
Now we corrected  the sampling procedure. But we want to reset the sample so that we can assign the changed Inspection Plan in Qa02.
But Reset sample is not happening. Please advice.
Thanks and regards,
Brijesh

how to remove the status of INSP, RREC. Can we undo the results recording?
--->you can not Undo Result vrecording hence can not change/revoke INSP, RREC status.
how to cancell the Inspection Lot?
--->Cancelling the original document can cancel the Inspection lot ( is lot is stock relevant means with SPRQ status).
Cancelling the lot  will just ensure that new lot to be can be cretaed for same Order( purchase order/production order etc).
You can identify cancelled  lot by LTCA status.

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    <ORACLE_HOME/ifs/custom_classes/oracle/ifs/server/renderers
    That should do it.
    Regards
    Mark D. Drake
    null

    Moving to Top

  • Buffered event counting. Why can't I explicitly sequence generating the Sample Clock Pulse and reading the counters?

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    Attachments:
    AfterPulse.vi ‏51 KB
    InSeparateSequence.vi ‏49 KB

    Kevin, thanks for all the work.
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    >from what I remember, there isn't much to it.  There really aren't many candidate places for trouble.  A pulse is generated with DIO, then a single sample is read from each counter.  -Yup, you got it. This should be trivial.
    >A timeout means either that the pulse isn't generated or that the counter tasks don't receive it. - Or it could mean that the counter task must be in the middle of executing when the rising edge of the pulse arrives. Certainly the highlighted execution indicates that. Making a broken vi run by cutting the error wires that sequence the counter read relative to the pulse also seems to support that.
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    >Wait!  I think that's it!  If I recall correctly, you're generating the digital pulse on port0/line0...  On a 6259, the lines of port 0 are only for correlated DIO and do not map to PFI. -But I'm not using internal connections, I actually physically wired P0L1 (pin 66) to PFI0 (pin 73). It was port0/line1, by the way. And when running some of these vi's, I also physically jumper this connection to port0/line2 as an analog input to watch it. And, again, the pulse does cause the counter to operate, so it clearly connects - it just doesn't operate the way I think it is described operating.
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    Attachments:
    NestedSequences.png ‏26 KB

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