Pulse train generation - questions about PLL and jitter

I need to generate a pulse train having a pulse width of 20ns and a period up to 100ms, selectable by software.
The jitter requirement of the period is 10ppm (1us over 100ms).
I thought to use PCI6221 to generate this pulse train but I could not find all answers in its documentation or anywhere else.
1. Can the PLL be used to get a clock frequency to the counters of 50MHz out of the internal clock of 80MHz (5/8 factor)?
2. Can the counters be set to output a pulse width of a single clock period in "Pulse Train" mode? (then the above 50MHz clock gives the 20ns pulse width).
3. The datasheet states the base clock accuracy is 50 ppm, in "Frequency Generator" mode. What is the clock period jitter in "Pulse Train" mode, including the PLL effect?
Is there any other counter/timer board that may be better for this job?
Thanks.

For this task first let’s take a look at the counter
specification of the 6221.
3. The datasheet states the base clock accuracy is 50 ppm,
in "Frequency Generator" mode. What is the clock period jitter in
"Pulse Train" mode, including the PLL effect? NI 622x Specifications
page 9 states as you said 50 ppm for the “Frequency Generator” for the pulse
train mode it will be the same 50 ppm as it is stated I below the: “General-Purpose
Counter/Timers” title.
I hope this knowledge base helps: How
Do I Change The Frequency Output Of My Pulse Train On The Fly?
You will not be able to generate a 20 ns
pulse, since you can only derive integer multiples of the 80 MHz time base in
this case, 1/40MHz pulses will be the closest you can get to a 20 ns
pulse. Also another note is that the
frequency generator does not have a selectable pulse width, it is a 50% duty
cycle signal.
For more information look at the M Series User Manual page 7-21.
Two other products that you might be
looking at are High Speed Digital Inputs and Outputs and Function Generators;
take a look at those and post on the right discussion forum if you have any
questions.
Message Edited by Jaime F on 05-05-2008 05:38 PM
Jaime Hoffiz
National Instruments
Product Expert
Digital Multimeters and LCR Meters

Similar Messages

Pulse train generation fails with certain values for "number of samples"

I'm generating a retriggerable analog output signal, and so I'm using a counter as the sample clock (see: Retriggerable AI Using Retriggerable Counter). I am finding that, above a certain number of samples, and only for certain values of the number of samples, the counter task gives me error -200305, "Desired finite pulse train generation is not possibe." The error crops up only when actually starting the task.
The analog signal that I'm trying to generate will be about 800 kHz, so my counter is set to run at the same frequency. I find that the counter task works fine if the number of samples to generate is anywhere between zero and 671,088 samples. Setting the number of samples to 671,089 gives the error above, as does 671,090 samples and so on. However, using 671,096, the counter task works fine. After that, the counter seems to output fine only if the number of samples is divisible by 8.
The only thing I can think of is that (617088 samples) / (800000 Hz) = 0.839 s. At the internal clock rate of 20 MHz, 0.839 s is 2^24 samples, and it is a 24-bit counter on this hardware. So if it's this internal counter rolling over, that's fine and I can work around that. But if that's the case, what I don't understand is why increasing the number of samples in increments of 8 samples still works.
The hardware is a PXI-6733 board, running with LabView 7.1.1 and NI-DAQmx 8.1.

Hmmm, multiples of 50 & 100? Now I'm puzzled again.
Here's how to make sense of the 100 kHz timebase idea though, even if it turns out not to be the right explanation. For a retriggerable finite pulse train, you actually use a pair of counters. If you were to program it manually, you could set your output counter to generate a continuous pulsetrain at 800 kHz using the internal 20 MHz timebase. This output counter would also be configured to use the other counter's output as a digital level-based pause trigger. So the 800 kHz pulsetrain is only output while the other counter's output is, say, high.
The other counter is configured for retriggerable pulse generation. The pulse duration or high time should be set for (# pulses) / (800e3 pulses/sec). This other counter can be configured to use the 100 kHz timebase, so its high time would then have to be an integer multiple of 10 usec.
So let's see... An 800 kHz pulsetrain is possible with a 20 MHz timebase (exactly 25 cycles). A 700 kHz (28 + 4/7 cycles) or 900 kHz (22 + 2/9 cycles) is not. So when you request those other frequencies, you actually get a near approximation. I dunno if DAQmx can be queried for the actual value correctly or not -- I recall an early version that reported back whatever freq you had asked for rather than what it actually used. Queries based on ticks (rather than time or freq) did return what was actually used, as I recall.
Let's suppose a request for 700 kHz gets truncated to 28 cycles of the 20 MHz timebase making a 1.4 usec period. Then 50 of those periods becomes 70 usec, which is evenly divisible by the 100 kHz timebase. Bingo! (Note: 70 is the least common multiple of 10 and 1.4)
Now suppose the request for 900 kHz turns into 22 cycles of the 20 MHz timebase, or a 1.1 usec period. Now it takes 100 of those periods to get to 110 usec, which is also evenly divisible by the 100 kHz timebase. Bingo again! (Note: 110 is the lcm of 10 and 1.1).
Did you follow the method here? It should help you figure out expected results for various output freqs and #'s of samples.
-Kevin P.

Need to unreserve a counter in a finite pulse train generation

Hi. Let´s introduce my application first: I´m trying to generate a N-pulse train with the M series PCI-6221, in order to achieve a high frequency clock for an SSI transducer. That´s why i can´t use a software generation (because of the high frequency) and i have to use a finite pulse train. Besides, I would need to use another counter for a variable and finite count (but not simultaneously). The problem is that, as i think i have understood, this finite pulse train involves the two counters working together, so I can´t programm another task with that resources.
My question is, Is there any way to do the finite pulse train generation, unreserve the counters, wait for a finite count to finish and so on?
Thanks.

Hello,
My knowledges tell me that you need two counter to generate a finite pulse train.
The first counter generates a pulsed of desired width and the second counter generates the pulse train which is gated by the pulse of the first counter (Counter 0=Pulse Generation, Counter 1=Pulse train generation).
However, the finite pulse train generation and the continuous pulse train generation seem similar. The key difference is the generation mode from continuous to finite and the use fo a DAQmx Wait Until Done vi instead of a loop to monitor user input. From a point of view of the hardware there is a difference between the two. Continuous pulse train generation requires only 1 COUNTER.
Maybe you can try with a continuous pulse train generation and with this method you have another counter to do a finite count.
Regards
DiegoM.

Two retriggerable pulse generations after a pulse train generation

I am trying to generate 3 pulse trains (ABCABCABC...) one after another.
The program currently I am using generates 2 pulse trains (ABABAB.....).
I am using the Traditional NI-DAQ and PCI-6602.
I am thinking about using pulse train generation first and then retriggerable pulse generation after that.
I understand that the retriggerable pulse generation can generate a pulse train triggered (or gated) by other counter output.
I have attached a test vi.
It uses the pulse train generation code when the counter number is 0 and when the counter number is not 0, then it uses the retriggerable pulse generation code, which I tried to modify from the pulse train generation code.
First of all, I am not sure if I wrote the retriggerable pulse generation code correctly.
Secondly, I don't know if the whole code will generate ABCABCABC...
I would really appreciate your help.
pchemjjang

pchemjjang,
I believe I may have misunderstood your original concern. It sounds like you want to output this finite pulse train on three different counters. You will output these pulse trains for 10 minutes and cease your program. The Finite Pulse Train.vi will output a pulse train from only one counter. With this Traditional DAQ example you would need to have three of these Finite Pulse Train.vi programs running simultaneously in parallel to output from 3 counters. I would strongly recommend using DAQmx for this application because you will only need to utilize 4 VIs. The rest of the work is done behind the scenes. There is an example in DAQmx which should accomplish exactly what you are looking for in one program. You must make sure to make the number of pulses 2000000, the duty cycle as 1/3 and the frequency as 1/(300us). The DAQmx driver can found here. In terms of the counters, I believe that each task requiring two counters will use the counter adjacent to it. If you would like to output on counter 0 using finite generation then counter 1 will be used as the gating counter. When you have the DAQmx driver then you can find this example by selecting Help>>Find Examples and then expanding Hardware Input and Output>>DAQmx>>Generating Digital Pulses>>Gen Dig Pulse Train-Finite.vi. I have included an image to show how the front panel of this example should be configured to work. The major note to make is that you will need to configure all of the counters in the channel names list. In Traditional DAQ this did not seem possible. In Traditional DAQ you would need to create a subvi out of the Finite Pulse Train.vi run three copies of it, in parallel, in a larger program. Please let me know if you will be able to utilize DAQmx in this application.
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Digital Support - Product Manager
National Instruments
Attachments:
Counteroutput.jpg ‏49 KB

Finite pulse train generation?

i am trying to generate a very specific pulse with my tio-6602 in labwindows. after a 20us delay, i want the board to generate 20 pulses, with a width of 1 us and an interval of 5us. ideally, this would be retriggerable at 100 Hz. any suggestions on what would be the best way to approach this problem?

Paco,
You can use a gated pulse train, which is similar to finite pulse train generation. With finite pulse train generation, you have one pulse for the gate of a counter set to generate a pulse train. The pulse train will only be output based on the gate, so if one pulse appears, you have a finite pulse train. Now, if you make the gate be a pulse train itself, then you can continuously output bursts of pulses. For instance, you can set it up such that the pulses are output when the gate is high. When the gate is low, the counter pulses would pause and when the gate resumes to the high states, your pulses would continue. I've attached a code excerpt for using NI-DAQ function calls to generate a finite pulse train that is in our database. I will see abo
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Applications Engineering
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http://www.ni.com/ask
Attachments:
finitepulsetrain.txt ‏2 KB

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I was wondering if there is a way to generate a pulse train with a width that is less than 2 milliseconds using labwindows 7.0 and a PCI-6602, I need more precision.
Derek

I use LabVIEW, not LabWindows, but I know that the 6602 device can certainly generate a pulse train with a width of way less than 2 msec. Way less than 2 microsec even. As low as 25 nanosec in fact.
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hi guys,
this has probably been solved a hundred times but i just couldnt find it!!
i have a pulse train generation happening on my ni usb-6211... using FREQ OUT, using a divisor on this, and routing it to PFI4.
id like to update my VI so i can specify the number of pulses....
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pulse train generation.vi ‏25 KB

Hi,
No problem at all, we are here to help. What I’m going to do first is to point you to a bunch of examples for that might give you a better insight of the capabilities of the card in terms of finite pulse generation. What you should be looking at is called retriggerable pulse generation and here are some examples to look at: Retriggerable Finite Pause Trigger Digital Pulse Train Generation, Creating a Delayed, Retriggerable and Finite Pulse Generator, DAQmx - Retriggerable Pulse Train Generation - LabVIEW - CVI - ANSI C - VB.NET - C#.NET and Retriggerable Finite Pulse Train with Changing Pulse Specs.
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Pulse train generation - questions about PLL and jitter

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