Pxi 6220 redefining terminal routes

Hello,
In MAX explorer, the pxi 6220 routes tab shows a direct route from PFI6 to the counter 1 gate (ctr 1 to be used for low freq counter) and an indirect route through counter 1 to PFI 4. But from the terminal diagram for the card, it looks like PFI 4 IS the counter 1 gate.
However, in LabVIEW terminal rerouting VI, I can select PFI 6 as the source and PFI 4 as the destination (there is no option to select counter 1 input as destination), but the counter does not appear to be counting. At the moment the input on PFI 6 is a "TTL" level square wave, but I don't get any counts.
Does anyone have any experience with this...any suggestions on what to try to determine where the problem is?
Best Regards,
Chris

Hi Chris,
If you are unable to see properties in your property node, I would first
check to see if you are filtering the properties according to the devices in
your system. There is a KnowledgeBase article outlining the property filtering
which can be found here.
Also, if you right-click the section of the property node where the
property is displayed, you should see a selection at the bottom titled “Select
Property…” If you click this, a browser should appear with all the properties
of DAQmx Channel.
If you are unable to select the property by right-clicking on the
property node, you can also navigate to View » Class Browser and select the
DAQmx object library and DAQmx Channel class. Hope this helps,
Daniel S.
National Instruments

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DC crosstalk between PXI 6220 channels due to high source impedance

Dear all,
I’m trying to digitize 10 single ended signals simultaneously with the PXI 6220. The source impedance for each signal is 1.5meg which should not be problem since the input impedance is >1G. Bias currents are taken in account and give only an offset error (assuming that they are constant). Crosstalk according datasheet is -75db at 100khz which is fairly okay for my app however the source impedance is not indicated for that specification. When I acquire data (Dc voltages) from the PXI6220 i see unexpected high crosstalks (again source impedance 1.5meg). The sample rate is 200Hz and I connected only one AIGND pin to the reference of the system. I verified whether the GND is okay by connecting one input pin directly to 5V (Rout=0) . This channel indicates 5V while the others (Z=1.5meg and grouded) give non -zero value of voltages (2V). DC leakage between channels in the cabling is not verified yet.
1)      Does anyone have a clue why I observe so much DC crosstalk at high source impedances.
2)      Does the PXI6220 digitizer have 16 parallel channel or does it make use of an multiplexer.
3)      Do I have to connect all AIGND’s to my system’s reference or is just 1 okay.
Patrick

Patrick,
I think the culprit is probably the multiplexer and not the amplifier input impedance. Look at the settling time graph on page 2 of the speicifcations. At 100 ppm error (which several source impedance curves cross) the settling time increases exponentially with the source impedance. 4 us at 1kohm, 6 us at 2 kohm, 13 us at 5 kohm, and 25 us at 10 kohm. It is probably not a reasonable to extrapolate that data more than two oreders of magnitude, but it is not unreaonable to expect some problems even at your slow sampling rate.
The user manual has this to say (pg 4-7):
M Series devices are designed to have fast settling times. However, several
factors can increase the settling time which decreases the accu racy of you r
measu rements. To ensu re fast settling times, you shou ld do the following
(in order of importance):
1. Use Low Impedance Sources —To ensu re fast settling times, you r
signal sou rces shou ld have an impedance of <1 kΩ . Large sou rce
impedances increase the settling time of the NI-PGIA, and so decrease
the accu racy at fast scanning rates.
Settling times increase when scanning high-impedance signals du e to
a phenomenon called charge injection. Mu ltiplexers contain switches,
u su ally made of switched capacitors. When one of the channels, for
example channel 0, is selected in a mu ltiplexer, those capacitors
accu mu late charge. When the next channel, for example channel 1, is
selected, the accu mu lated charge leaks backward throu gh channel 1. If
the ou tpu t impedance of the sou rce connected to channel 1 is high
enou gh, the resu lting reading of channel 1 can be partially affected by
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If you r sou rce impedance is high, you can decrease the scan rate to
allow the NI-PGIA more time to settle. Another option is to u se a
voltage follower circu it external to you r DAQ device to decrease the
impedance seen by the DAQ device. Refer to the KnowledgeBase
docu ment, Decreasing the Source Impedance of an Analog Input
Signal , by going to ni.com/info and entering the info code rdbbis .
A buffer per sensor is the best fix.
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Can we lock 80 MHz timebase to PXI_CLK10 on PXI-6220 M Series DAQ?

I am using PXI-6220 to measure Frequency/Period of 32768 Hz clock signal, accuracy is very important. I have provided signal to measure on Gate input of Ctr 0 (PFI 9). I am using 80 Mhz Timebase. I want to Lock PLL to PXI back plane 10 MHz reference (PXI_CLK10) which in turn is locked onto the 10 MHz reference via PXI-5600 on Slot 2 (External 10 Mhz standard is connected). so far I don't see a way to lock PLL to PXI_CLK10. Is that possible at all? see the image attached to this message.
Attachments:
M Series DAQ Question.png ‏62 KB

Hello Abhatti,
Based on the diagram that you have attached, the M-Series card can PLL to a higher accuracy clock such as the PXI Clock_10. The way to configure this change using the DAQmx driver is route the signals using the DAQmx Timing RefClk.Src Timing property node. Once you place down this property node, and specify the RefClk.Src attribute, you select the PXI-Clk10 as your reference clock source. This will discipline the 80 MHz Timebase of the DAQ card to the 10 MHz reference clock of the PXI chassis. Which chassis are you using? Also, how have you PLL'ed the 10 MHz backplane clock to the PXI-5600 Downconverter?
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Redirecting Voip call to another termination router

Hello All
The structure is very simple: There is one originating router (as5300 let say A) and
one terminating router (as5300 let say B) with 1 pri line. I want to route some calls whose have specific destination pattern from B to another router (let say C) to be terminated.
I have used "dial-peer voice xx voip" with "session target ipv4:x.x.x.x. on B.
But it failed. When I debug it on B ,it gives " can not gateway with C".
Do you think the idea is wrong for this structure . or how can I do this ( PS :I can administrate only termination routers )
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to tapatel:
First of all thank you for your assistance
Router B is not making call origination, it is only termination router.
Router A (I do not manage router A), is sending voip calls to B and I want to route some calls which has specific destination pattern from B to C. The configuration for B is like this:
! the dial-peer 101 and 99 below is working properly
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dial-peer voice 99 voip
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dial-peer voice 102 voip
destination-pattern 30549238.....
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Repetative trigger from PXI-6733 to PXI-6220

I am running a PXI-6733 in continuous mode and want to send a trigger pulse from the 6733 to a PXI-6220 at the start of each cycle. I will also want to do this in finite sample mode. I have used a DAQmx Connect Terminals VI to connect the trigger channels. But I cannot find how to set the 6733 StartTrigger as an output or how to synchronize it with the analog output. Any suggestions would be welcome.
Bob

Since your AWG needs to send the 6220 the trigger, the M Series (6220) correlated DIO feature doesn't help. Luckily, the 6733 also has the feature. I've attached a vi that shows how to set up the 6733 to output a companion digital waveform to the analog waveform. The first point in the digital waveform is a 1, the rest is 0. You will have to connect a physical wire from the digital line used to an input (PFI) of the 6220.
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Attachments:
6733 Correlated AO and DO.vi ‏66 KB

About PXI-6220 PXI-6221

We want to use PXI-6220 or PXI-6221 to design a system. And we will use the CVI or Labview, but we cannot find the PROGRAMMING MANUALS of PXI-6220 or PXI-6221.Where can I get them? Thanks!

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Learn 10 Functions in NI-DAQmx and Solve 80% of Data Acquisition Applications
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NI-DAQmx Help (User Manual)
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PCI 6220 how to route I/O signals?

Hi
I am using a PCI 6220 connected with a SCC 2345, on labview 71 XP based.
I have 24 V signal and I want to divide the frequency, and send out divided signal on RTSI 0.
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PXI 6220 - problems with the counter

Hello all,
I try to make a buffered counting with counter0 of my PXI card 6220, to count the speed of a motor through a photocell and a sticker over the pulley of the motor.
I have wired my photocell at PFI8 (source) and I generate a pulse train that I have wired in PFI9.
The input to the counter is a pulse train 5V high level - 0V low level.
The problem is that the counter counts sometimes more than 1 pulse for every turn of the motor. However, apparently the pulse train looks ok.
I don´t know what´s the problem.
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Thank you very much in advance!!

Pete;
I agree that is a little strange.We don't have such problem reported on our Data Bases.
A workaround you can try is to make a sinle pulse goes to the source, before start the buffered acquisition, and see if that makes the counter keeps reporting a 1 value.
You can also try the same thing on another counter of the board to see if that problem is related to the counter you are using.
Regards
Filipe A.
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National Instruments

Regarding NI PXI-6602 - How to route PFI_33 to a grounded DIO Line.

The PXI-6602 card with the TIO chip seems to be very robust on counter and DIO pin assignments and routing, but I have found that counter 1 has a pin (PFI_33 -AUX IN (UP/DOWN) ) that has been troublesome. I need to either route this pin to another pin such as a DIO pin set as an output and pulled LOW or be able to manipulate the pin to a low state when I setup counter 1. This is to ensure that noise is kept to a minimum due to the PXI-6602 being cabled to a board with a PLD on it. Any solutions on how to tie PFI_33 low?
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B Spears,
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Thanks!

Hello,
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LA

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Query on NI PXI 6602 Timing I/O Module

How to configure the PXI 6602 Timing I/O module to generate frequency on 8 lines and measure the frequency using the same card?

To me, the pinout is pretty clear so yes, the PFI lines and P1,P2 are related.
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Attachments:
pxi-6220.PNG ‏36 KB

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Pxi 6220 redefining terminal routes

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