PXI-6682 Reports Altitude incorrectly

I am using a PXI-6682 to track position and it is reporting my altitude (3rd floor of building at sea level) as being 15 to 30 meters below sea level. The altitude measurements vary quite a bit with time while the latitude and longitude are stable. Why am I getting these results and is there any thing I can do to improve it?
Thanks,
Bruce

Bruce,
The altitude accuracy of GPS is notoriously worse than the horizontal accuracy. This is due to fundamental geometric limitations, but it can be exacerbated by poor satellite reception, so make sure your antenna has a clear view of most of the sky.
As an example, I have a nice little handheld Garmin receiver, which does very well for horizontal position but is quite often off by several hundred feet of altitude. Fortunately, it also has an aneroid barometer for measuring altitude. Interestingly, since it has no way of knowing the actual sea-level pressure, it gently calibrates the barometer over the long term by averaging the GPS-derived altitude data over time. This seems to work fairly well, and as a result it's always right to within a few dozen feet.
If you're sure your antenna is well-positioned, you might try averaging the altitude data over time.
Hope this helps,
Ed

Similar Messages

PXI-6682 + multiple Serie S & M cards cause timestamp delay

I'll try to give as much info as possible and hopefuly someone will have an answer to this problem.
Language: C++
Introduction:
1- I have (1) PXI-6682 (Timing card), (6) PXI-6143 (Serie S (8 analog inputs each)), and (2) PXI-6224 (serie M (8 analog inputs each))
2- Every card is a task (so that's 8 tasks
3- Every card is in sync (they give data equal...more or less... to one another
PROBLEM:
1- Timestamp is off by up to 200 ms (not drifting...simply off by a set number of ms)
2- Every call to niSync_ReadMultipleTriggerTimeStamp gives me a timestamp off by that much
I don't have any info on how the tester managed to know it was 200 ms off, my theory is he tested it with some older equipment to validate the new one

Hello there,
Kindly help me with DAQmx Time stamp related problem as described below.
Setup : PXI 6133 Qty 4 (Slot 3, 4, 5, 6)
PXI 6255 Qty 1 (Slot 2)
PXI 6255 doing a Continuous Acquisition at 1 mSec Sampling and 1000 samples/iteration.
PXI 6133 doing a Ref Triggered Acquisition at 1 uSec Sampling interval and Pre and Post Trigger samples of 100000 Samples each.
Test : PXI 6133 - Reference Trigger Configured on PFI 1 line of First PXI 6133 card.
input Signal given to AI 0 OF First PXI 6133 card.
All PXI 6133 cards are included in a single task.
PXI 6255 - Input given to Channel 0 AI
External Function generator - One Digital Trigger generated of width 50 mSec High Interval.
Another signal generated for input to above cards. (Square wave of 10 mSec Period - 5 periods generated on the rising edge of trigger)
So It means When I acquire square wave in my waveform, I can consider rising edge of square wave as a rising edge of trigger (as both signals are generated aligned from external function generator)
I have attached Screenshots and programs I have used for that.
Problem: As both singal are generated at a same event, Both 6133 and 6255 should acquire that singnal at a same timestamp.
I have also read related documents about timestamp but I could not succeeded to find any link in this.
I am getting square wave 100 msec earlier in 6255 then of 6133.
If I used only single card of 6133 then that inaccuracy of 100 msec is shifted to 25 msec.
Please help me as soon as possible.
Attachments:
Timestamp mismatch between 6133 and 6255.docx ‏377 KB
Timestamp mismatch in 6133 & 6255.zip ‏70 KB

Using PXI-6682(H) in PXI Express chassis to replace backplane clock

I have a PXI-6682H in a PXIe-1075 which I use for event timestamping. I also have a PXIe-6672 card in the timing slot.
I would like to replace the 10 MHz backplane clock to use the 6682 as a GPS disciplined oscillator and synchronize multiple PXI chasses.
I understand from the block diagram in the manual that the PXI-6682H does not possess the connection to directly replace the backplane clock as the PXI-6682 does in a PXI chassis.
Is there any way for me to replace this clock? Perhaps using an external connection? If so could you briefly explain how this would work and what software steps would be required?

Hello Gregoryng,
It might work since the PXIe-6672 and the PXIe-6674T are both timing and synchronization modules, but the best option would be the PXIe-6674T, which is able to work with other protocols such as GPS while the other cannot. It seems that in the video they use GPS.
I think the PXIe-6672 will not work for this with the PXI-6682H, but you can give it a try.
The one in the video seems to be a PXIe-6674T.
Regards.
Ernesto.

PXI-6682 read IEEE-1588 timestamp from 7953R over RTSI bus

Hi,
I am relatively new to LabVIEW
programming, although I have two years of hard experience using LabVIEW
FPGA tools.
So, I
have a PXI-1033 chassis, and I have plugged in an PXI-6682 IEEE-1588
card into slot 2 and a PXI-7953R card into slot 4. (Random selection
for slot 4) What I am trying to do is read the GPS timestamp from the
6682 card via the RTSI lines directly into the 7953R FPGA card.
Unfortunately, I have no idea where to start and what to read, and all
the examples (keywords: RTSI, IEEE-1588) that I find are for how to
read the IEEE-1588 timestamp inside the Host Operating system and
nothing tells me how to do it directly from the FPGA. My goal is to
build a machine that timestamps network packets that are being read by
the FPGA hosted inside the PXI-7953R card.
Can anybody point me in the right direction? I
basically want to learn more about RTSI, where the PXI-6682 outputs its
IEEE-1588 timestamp, and how data is transferred over the RTSI bus from
inside a PXI chassis.
Thanks,
John

Thanks for the response Alejandro,
I have a 7953R FlexRIO board with the Mimas Prevas Dual Gigabit Adapter Module (http://www.prevas.com/ethernet_simulator.html) plugged in. Ethernet packets enter the Mimas Dual Gigabit Adapter and then go directly to the FPGA as raw Ethernet frames.
From what you are telling me it seems like I cannot have a timestamp go from the PXI-6682 to the 7953R via the RTSI lines and to then be appended to the end of the ethernet frame before being retrasmitted out the other port of the Dual Gigabit Adapter. (With proper recalculation of the 32 bit CRC being done inside the FPGA of course)
I will do some more reading of the manuals and will then call NI Support.
Thanks again!

Can't replace PXI onboard clock with PXI-6682 oscillator clock on PXI back plane

I have installed a PXI-6682 timing module in slot 2 of a PXI-1031chassis with a PXI-8110 controller running Hypervisor and RT. The 6682 is installed on the RT system under Hypervisor for GPS timing during measurements but I would like to put the TCXO on the PXI-1031 chassis backplane (replacing the PXI onboard clock). When I try to run the "Route Clock.vi" that I found in the example finder, all I get are error messages indicating that a parameter for this operation is invalid. The source terminal is "Oscillator" and the destination terminal is "PXI-Clk10_In". How do I determine which parameter is invalid? Any suggestions? Thanks
Solved!
Go to Solution.

Hi vugt,
I tested this out and have what I believe to be your final answer.
The short answer: The PXI-6682 can be used with NI-Hypervisor on the Windows side, but not on the Real-Time side.
The long answer:
While the NI-Hypervisor Manager allow you to put the PXI-6682 on two different systems, it is still only one PXI card on the PCI bus, so really only one system can access it at a time.
Therefore we need to assign both "devices" to either Windows or Real-Time. For our purposes, let's assume we assign it to Real-Time.
On an NI-Hypervisor system, each PCI interrupt line can only be assigned to one operating system. Either it can be assigned to Windows, or it can be assigned to RT.
Here is where the problem arises: The PXI-6682 needs to be located in a System Timing slot (generally slot 2). However, this slot (at least in the 1000B chassis I tested in) is located on the same PCI interrupt line as the chipset. Windows is required to have access to this PCI interrupt line, so devices used by Real-Time cannot be located on this interrupt line.
This prevents us from being able to use the PXI-6682 in Real-Time.
The NI-Hypervisor Manager will try to tell you to resolve this conflict by moving the PXI-6682 to slot 3, however, now the System Timing slot requirement is not met.
This does not prevent the card from being used on the Windows side of an NI-Hypervisor system, or on a purely Real-Time system.
Have a great day,
Chris V
Applications Engineer
National Instruments

PXI-6682 GPS coordinates...

Hi All!
Can I obtain GPS coordinates from the PXI-6682 board?
Jury

Hi!
Thank you very much!
Jury
Attachments:
GPS.JPG ‏74 KB

Help! PXI-6682 timestamping is limited to 2.5Hz

I am outputting a 30Hz signal from a pulse generator, and I have reduced the vi to the bare minimum, but the program still only logs a timestamp about 2-3 times a second. Checking timestamping in ni-max test panels has the same result. The cables are fine and I've tried PFI0, 1, and 2. What's going on?
Attachments:
timestamp_check3.vi ‏18 KB

Hi Steve-
     You have selected 'Read Single Timestamp' as the polymorphic instance of the niSync Read Trigger Timestamp.vi. Change that to 'Read Multiple Timestamps' from the drop-down menu. This will enable you to pull an array of timestamps from the 6682, as opposed to just a single timestamp, as you had it configured. The reason you were only getting 2-3 Hz is because you were pulling only a single timestamp with every iteration of the while loop, which was only iterating at 2-3 Hz. With the Multiple Timestamps enabled, your while loop will still iterate at 2-3 Hz, but you can pull several timestamps with every iteration. To specify the number of timestamps to pull, right-click on the number of timestamps input and select Create»Constant. Start out with 10 as the constant and increase from there until you are pulling 30 timestamps every second. Be sure to also wire a timeout value to the timeout input as well (ten seconds should be sufficient, but you can fiddle with this number also).
     Your number of timestamps indicator will now be the 'detected edges' output of the niSync Read Trigger Timestamp.vi instead of the number of loop iterations. Be sure to also place an niSync Close.vi at the end of the program to properly close the niSync session and clear it from memory.
     This should now run how you want it to. I hope this helps, and best of luck with your application!
Gary P.
Applications Engineer
National Instruments
Visit ni.com/gettingstarted for step-by-step help in setting up your system.

How to set a DMA transfer type for PXIe-6536 in LabWindows/CVI?

I have a PXI chassis PXIe-1078 with a controller PXIe-8115 running under Windows 7. The digital output board is PXIe-6536.
I use a function DAQmxSetChanAttribute to set a property DAQmx_DO_DataXferMech to a value DAQmx_Val_DMA, since I want to use a direct memory access data transfer. This wokred well with a PCI-6534 board using the same LabWindows/CVI code before migrating it to the PXIe system.
Unfortunately, running this code on the PXIe system reports a DAQmx error -200452: "Specified property is not supported by the device or is not applicable to the task".
The task is created in the following simple way (the board name in MAX is 'Dev1'):
   DAQmxCreateTask ("digTask", &digitalTask);
   DAQmxCreateDOChan (digitalTask, "Dev1/port0:3", "DIG_CHANNELS", DAQmx_Val_ChanForAllLines);
   DAQmxSetChanAttribute (digitalTask, "", DAQmx_DO_DataXferMech, DAQmx_Val_DMA, 15);
How can I solve this problem? How is it possible to choose between different transfer types?
Thank you in advance for any hint!

Hi CavityQED,
The PCI-6534 is a "Digital I/O" board while the PXIe-6536 is a "High Speed Digital I/O" board, that's why they don't have the same properties.
By the way you can use DMA transfer with this method :
http://zone.ni.com/reference/en-XX/help/370520J-01/hsdio/direct_dma/
Let me know if it helps you.
Regards.
Mathieu_T
Certified LabVIEW Developer
Certified TestStand Developer
National Instruments France
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Function control of the PXI system

Hi All!
We order NI PXI-1036DC + PXI-4462 + PXI-6682 GPS + PXI-6653 + PXI-8101.
Is it possible to control:
1. DC voltage and current?
2. GPS coordinates of the system?
3. Accuracy (or quality) of the 10 MHz clock disciplining by the 6682 GPS? It may be accuracy of the GPS positioning or number of satellites.
4. Temperature? It may be processor temperature.
Jury

Hello Jury,
Thank you for bringing this issue to the forums.
Regarding your questions:
1. What do you want to control the DC voltage and current of? Which card exactly?
2. I am not exactly sure what you mean by controlling the GPS coordinates of the system. Can you please explain further?
3. You can find the specifications of 10 MHz clock and accuracy of the GPS on page A-5 and A-6 of the PXI-6682 GPS Manual: http://www.ni.com/pdf/manuals/372292b.pdf
The 10 MHz clock accuracy is +/- 1 ppm, you cannot change this value. The accuracy of the GPS is within 15 ns, you cannot change this value as well. Once again all this information can be found on page A-5 and A-6 of the PXI-6682 GPS Manual.
About the number of satellites, the more satellites available to the receiver, the more precisely it can determine time and location. Therefore, the location of the antenna should be such that it will receive signals from the greatest number of satellites possible.
4. The +/- 1 ppm accuracy of PXI-6682 is specified in the range of 0 to 55 C.
Thank you,
Vimal Fernandez
Applications Engineer
National Instruments

Can't install NI-sync and others on PXI-8101RT

Hi All!
I have PXI-1036DC + PXI-8101RT + PXI-6682 + PXI-6653 + PXI-4462 + PXI-6143. I try to install NI-sync 3.3.5 and Multifunction DAQ & DSA 9.7.0 on 8101RT and obtain the message, that this components requires MIG String 2.3.0.
What is the MIG String and where can I take it?
Jury
Solved!
Go to Solution.

Hi,
Which version of LabVIEW are you using? I noticed that NI-SYNC 3.3.5 is supported for LabVIEW versions 2009 and above.
Try to navigate to C:\Program Files (x86)\National Instruments\RT Images\NI-DAQmx, open the file nimigString.cdf with a text editor. If the version is 2.2.1 then modify it to 2.3.0.
If you are not able to find the previous file, try to install DAQmx first.
Regards,
MCOTO

6682 1588 synchronisation

Hi!
I'm trying to synchronize two PXI chassis with 1588 clocks. To achieve this i use 2 PXI 6682H boards.
I created a test program which:
- init the 1588 (init the clock, set time reference , start the participation in the 1588 network)
- wait to be synchronized (only the slave)
- create the clock at a round second.
The 2 clocks are synchronized (+/- 10 ns) but the problem is the phase ( 0 -750 ns). I watched the 2 clock with a scope and if i run severeal time the same program i have a phase error wich vary from 0 to 750 ns. The clock frequency is 1,5 MHz.
I don't understand , normally when i create the clock, the two clocks are synchronized, however i can have 750 ns error ...
Any idea welcome ...
Solved!
Go to Solution.

Hi.
There are a couple of things that I can think of that could result in the behavior like what you are seeing
The first is if the clock generation was started before the slave had made its initial timekeeper adjustment to match the master. It is easy to verify if this is the problem: when you see frequency-locked, but out-of-phase clocks, can you stop clock generation and re-start it? Do you see the same offset? Of course, when stopping-re-starting clock generation, 1588 operation should not be interrupted (use the "niSync Create Clock" and "niSync Clear Clock" VIs).
Another thing that could cause this is if the start time for each clock is in a different second's boundary. Since the period of a 1.5MHz clock is such that you don't have a whole number of periods within a second, if you start clk A at time 9:00:00 and clk B at time 9:00:01, the clocks will have an offset. Additionally, the PXI-6682 can only generate clocks with periods that are a multiple of 10ns. The period of a 1.5MHz clock is 666.6666... ns. The NI Sync driver will round this up to 670ns, so the offset of clocks started at different times can be as high as half of that (335ns).
I know this would not explain the larger (up to 750ns) offsets you have seen, but I hope this can help in finding the issue.
Regards,
Alejandro

Monitor IEEE1588 network two 6682 boards

Hello,
I have a distributed application synchronized by means of IEEE 1588 over a switched network. In order to monitor the health of the network, I use two PXI-6682 boards, one acting as a master clock and the second as slave connected through an Ethernet switch and monitor the time jitter between a 1PPS signal generated on both boards. This would ideally be a feature of my master clock node itself for which I would ideally fit the two 6682 boards in the same chassis, configure one as master clock, the other as slave clock and connect both to my Ethernet switch.
The PXI controller gets confused if I insert the two boards on the same chassis. I have not found any information on how to manage this configuration or whether this is altogether possible.
B.

Hello,
Thanks for your input. I appreciate your help. I needed to do something a bit different but it eventually solved the issue:
On the XP Device Manager ,
- Uninstall the two PXI-6682 devices under Data Acquisition Devices
- Uninstall the two AMD devices under Network adapter
- Scan for new Hardware
- Disable the two PXI-6682 devices under Data Acquisition Devices
On MAX,
- Delete the broken PXI-6682 under NI-DAQmx Devices
On the XP Device Manager,
- Enable the two PXI-6682 devices under Data Acquisition Devices
On the good side, the issue is solved and the configuration survives the controller reboot. On the other side, I am very worried about having to apply such tricks to get this system working.
Cheers,
B.

Synchronize 2 PXI Systems through GPS using PXI 6552

I want to synchronize two PXI systems separated by a distance of 5kms through GPS.
PXI 6682 is a timing and synchronization card which can be used to achieve this. I also have a requirement to use PXI 6552 HSDIO in my application. Few channels in PXI 6552 are free. So i want to know if it is possible to achieve GPS Synchronization of the two PXI systems using PXI 6552.
Regards,
Sundar Ganesh

Hi Ryan,
This is a system configuration which i am doing for a requirement. The requirement is RF Generation in one PXI system and RF Acquisition in another PXI system separated by a distance of 2kms. The applications that will be running at both these PXI systems may be started at different times. So i am thinking of using a PXI card in both the chassis to synchronize them through GPS.
Regarding this, i have already contacted the local NI FSE and together with him only we have decided to go ahead with PXI 6552 for GPS Synchronization. But i started doubting the usage of 6552 for GPS synchronization when i couldnt see the card in the list of Timing and Synchronization cards.
I have attached a schematic of the configuration. Let me know which PXI card should be used for synchronising these two systems.
Regards,
Sundar
Attachments:
PXI Configuration.JPG ‏21 KB

Code could not be generated because an external component or driver is missing

Greetings All,
     I've using Labview for a little over a year and I have an interesting situation with regards to Labview that I came across today. When I left off yesterday (01/11/12) my TestStand sequence was compiling fine. Today for some reason the compiler told me that one of the VI was broken or missing a sub vi. When I made my way through all the sub vi's in the vi that seemed to be a problem I came across "Code could not be generated because an external component or driver is missing".
     The problem started on the computer (NI PXI-8101 with WinXP and Labview 2010) located in a PXI-1044 that is in my Test Stand.  I have a complete backup on my laptop and my desktop computer which both compiling successfully with no errors. I tried installing the directory on another PXI-8101 and got a different set of results.  The first PXI-8101 gave 100+ errors in TestStand pointing to one of my vi's and the other PXI-8101 reported only one (1) error. The vi is basically using DAQmx vi's to create a "write to one line" action. I'm kind of stumped as to why it works on the laptop/desktop and not the PXI computers. All four computer are WinXP professional and Labview 2010. I saw somethings through google search engine but nothing conclusive. I'm hoping that someone can give me an explaination as to what is causing the error as described. Even if I copy over the directory it doesn't fix the problem. Thank you in advance for an information you provide with this rather interesting problem that I've encountered. If you require addition information let me know.
Regards,
Scott
Solved!
Go to Solution.

Greetings Beau,
     Thank you for the reply.
     I loaded the offending VI into Labview (2010) with TestStand inactive. Of course this was after I completely shutdown the computer and re-booted to ensure that nothing was resident in memory. I've included a couple of the error list boxes in this post.
     It comes down to a subvi that is two (2) subvi's deep. All these vi's are doing is commanding a write or read to and from the PXI-6509. When I check the VI at the level that has no broken run arrows (named below), nothing in the block diagram looks out of place as it should since these were installed by Labview installation. The vi that uses these vi's looks total normal and its block diagram doesn't have anything out of the ordinary yet the run arrow is broken. The odd part of this is that the top of the window that states the filename of the vi has an astrex at the end of the filename, even though nothing has changed in that vi.
Here is a list of the deepest level that has no broken run arrow:
DAQmx Create Channel (DI-Digital Input).vi
DAQmx Start Task.vi
DAQMX Read (Digital Bool 1Line 1Point).vi
DAQmx Clear Task.vi
DAQmx Create Channel (DO-Digital Output).vi
DAQmx Write (Digital U8 1Chan 1Samp).vi
     I guess the real question is what is the error message ("External component or driver missing") really telling me if all of the vi's look right. I appreciate any information you can send my way that will give me a better understanding of where this error is coming from. The program I developed had been running without a hitch for a month an all of sudden crash.
Thank you for your time in this matter.
Scott
Attachments:
Write to one port broken VI error list.JPG ‏47 KB
Readfrom one line broken VI error list.JPG ‏46 KB
Broken_VI_Error_Screen.JPG ‏56 KB

Setup of NI-TimeSync with MAX in LabVIEW 2010

Hi,
I have a set of PXI systems running LabVIEW 2010 RT and want to start using NI-TimeSync for my timestamping. My systems have NI-TimeSync 1.0.1 installed and NI-Sync 3.2.1 installed. I have a system with a PXI-6682 card in slot 2, and have succesfully gotten it to pull time from a GPS antenna.
When I go to MAX on any of these systems, I briefly see "Searching for time synchronization sources..." in the Time Settings tab, and then nothing. I don't see the fields shown in this screen shot:
http://zone.ni.com/devzone/cda/tut/p/id/11466
What am I missing?
Solved!
Go to Solution.

Hi all- it looks like there are two different issues occurring in this thread.
Tim Maddux; I believe you are referring to the Developer Zone tutorial that highlights some features we are scheduling for a future release of NI-TimeSync. We did place this one the web a bit early, but I'm glad you were able to find the material and start investigating the possibilities. You should be able to utilize those "views" in the near future
sachsm; I think you are referring to an issue where the PXI-6682 would not appear in MAX even with NI-Sync installed. This issue could intermittently (or more frequently as in your case) occur for our customers as it depended on how Windows loaded certain services. At a low-level, it was like a race condition that we were able to prevent by removing some dependencies. Regardless, you can either restart the nitsu service when you experience this issue or you can upgrade your driver to NI-Sync v3.2.2.
I hope this helps.
Regards,
Tyler C

PXI-6682 Reports Altitude incorrectl​y

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PXI-6682 Reports Altitude incorrectly