Qual a diferença do LabVIEW FPGA e o LabVIEW REAL- TIME?

Hello,
Could anyone help me? This question arose in my work and could not answer. Does anyone know tell me?
Thank you.
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Olá,
Com o LabVIEW FPGA você programa diretamente o chip FPGA presente no chassis cRIO, placas da NI Série R e single Board RIO. Você programa as E/S diretamente no chip, sendo assim uma programação de mais baixo nível. A grande vantagem do FPGA é o "paralelismo real", o que garante altas velocidades na execução das rotinas programadas.
Assista ao webcast Introduction to LabVIEW FPGA
Com o LabVIEW Real-Time você desenvolve aplicações que são críticas em relação a "tempo". Chamamos de aplicações "deterministicas". A idéia é que, se você tem uma rotina que deve ser executada em um tempo determinado, a diferença entre o tempo real e o que você programou seja o menor possível. Aplicações em Computadores comuns não são deterministicas, pois enquanto o LabVIEW executa uma certa rotina programada, o Windows está executando outras tarefas, monitorando a utilização de periféricos, atualizando a tela, etc.
Real time não significa "Velocidade", mas "Confiabilidade".
Assista ao webcast LabVIEW Real-Time: Graphical Development, Hard Real-Time Performance
Hello,
With LabVIEW FPGA you program the FPGA chip itself. The FPGA chip is found into cRIO chassis, NI R-Series Boards, and NI Single board RIO. You program the I/O directly in the chip, so we consider this as a low level programing. The main FPGA advantage is the "Real Paralelism", which guarantees high speed execution programming.
Whatch Introduction to LabVIEW FPGA webcast
With LabVIEW Real-Time you develop called "time crictical" or "Deterministics" applications. In case of you routine must be executed in a specified period of time, the difference between the real time execution and the time you programmed is as low as possible. Commom computers programming are not deterministic, because in the meantime of executing a certain programmed routine, the OS (e.g. Windows) is running other appication tasks, monitoring peripherals like mouse and keyboard, uptading screen, etc.
Real-Time doesn't mean "faster" but "reliable".
Watch LabVIEW Real-Time: Graphical Development, Hard Real-Time Performance webcast
I hope the information helps you!
Best Regards
Felipe Flores
Engenharia de Aplicações
National Instruments Brasil

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LabVIEW 7.0 utilize the real-time functions in Window 2000 Real-time.

Can an application written with LabVIEW 7.0 utilize the real-time functions in Window 2000 Real-time.

The LabVIEW DATA ACQUISITION HANDBOOK (not sure of the exact title), has examples of simultaneous I/O, which is what I assume you need.
Clock- controlled analog output (to drive the stepper), and analog input (to read your inputs), sound like the ticket for you.
You could load the output buffer with a pattern that drives your stepper, and get multiple input samples for every step, all precisely timed.
Steve Bird
Culverson Software - Elegant software that is a pleasure to use.
Culverson.com
Blog for (mostly LabVIEW) programmers: Tips And Tricks

Is vision development module in labview 8.6. sufficient for real-time image acquisition and analysis using a webcam

Hi,
I'm new to labview and trying to develop an eye-tracker using labview 8.6. It has the vision development module and i was wondering if this was sufficient for real-time image acquisition and processing or would i be needing any other software tools.
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Hello, certainly it is possible and sufficient for real-time tracking!
About eye tracking - if you need an example, you can find the code here:
https://decibel.ni.com/content/blogs/kl3m3n/2013/10/08/real-time-face-and-eye-detection-in-labview-u...
The code uses OpenCV functionalities along with the LabView UI (and some other functions like overlay).
Hope this helps a bit.
Best regards,
K
https://decibel.ni.com/content/blogs/kl3m3n
"Kudos: Users may give one another Kudos on the forums for posts that they found particularly helpful or insightful."

FlexRIO DRAM problem in Labview FPGA 2010

Hello,
I am just switching from Labview FPGA 2009 to Labview FPGA 2010 and I am having compilation problems with very simple projects that shouldn't fail to compile.
I am using a FlexRIO 7965R board as a target. Initially, I just wanted to recompile a project that was working fine under Labview FPGA 2009. When it failed, I drastically
simplified it to isolate the source of error. I ended up with what is attached. In this very simple VI I just write some values into DRAM banks in one timed loop, read them out in another and send them through a Target to Host DMA FIFO. Both loops are quite slow running at only 40 MHz. Previously, I was able to compile VIs with DRAM clip nodes in timed loops running at 100 MHz without any problems.
The compilation fails with this summary:
"Compilation
failed due to resource overmapping"
although it should fit easily.
The error is definitely related to DRAM. This s what Xilinx log says:
"ERRORlace:543
- This design does not fit into the number of slices available in this device
due to the complexity of
   the design and/or constraints.
   Unplaced instances by type:
     IDELAYCTRL    21 (48.8) "
Then it lists these instances (about 20):
   0. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate0
   1. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate1
   2. IDELAYCTRL Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate2
Both DRAM banks are configured with the clip node for 128-bit FIFO version v1.1.0. I also tried using the legacy version v1.0.0 but it didn't make any difference.
It looks like I have some configuration problems I can't identify or there is something wrong with the DRAM clip node in Labview FPGA 2010.
Any ideas on what could be happening here? Any help would be much appreciated.
Regards,
Ivan
Attachments:
flexrio_dram_test.lvproj ‏157 KB
flexrio_dram_test_fpga.vi ‏124 KB

Hello Ivan,
It looks like in your project you are using both the NI 5761 adapter module and DRAM. We have seen a few cases where certain combinations of DRAM, adapter modules, and FlexRIO FPGA targets in LabVIEW FPGA 2010 have caused some resource overmapping errors of the IODelayCtrl components used in the adapter module and DRAM CLIPs. Due to a bug, certain constraints inside of the CLIP cores are misinterpreted by the ISE compiler causing this overmap error when you switch to LabVIEW FPGA 2010.
This was reported to R&D (# 258076) for further investigation and to create a long term fix. In the meantime, for this specific issue please use the following knowledgebase article to apply a patch to your FlexRIO fixed logic files. This patch updates some of the constraints used by the DRAM to ensure that the Xilinx compiler can properly interpret them. There are more details on your issue in the knowledgebase as well.
Knowledgebase 5E4FNCDP: Error, “Compilation Failed Due to Resource Overmapping,” When Using NI FlexR...
If you do run into any other issues regarding IODelayCtrl components, feel free to reply to this forum topic to let me know about them.
Regards,
Browning G
FlexRIO R&D

How do I install Labview 64 bit support for the labview fpga module?

see subject.

Hi,
The LabVIEW FPGA Module uses the 32-bit version of the Xilinx tools, even on the 64-bit OS.
There is no 64 bit version of LabVIEW FPGA and you must have LabVIEW 32 bit
installed on your 64-bit machine to use the compatible version of
LabVIEW FPGA.
NI LabVIEW FPGA Module will run within the 32-bit emulation layer, Windows on Windows (WOW64).
regards,
Houssam Kassri
NI Germany

What are the differences between LabVIEW, LabVIEW RT and LabVIEW FPGA

I need a comparison of LabVIEW, LabVIEW RT and LabVIEW FPGA
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NI LabVIEW is a platform and development environment for a visual programming language from National Instruments.
NI LabVIEW Run-Time Engine includes the libraries and other files necessary to run applications and shared libraries built in LabVIEW.
NI LabVIEW FPGA Module uses LabVIEW embedded technology to extend LabVIEW graphical development and target field-programmable gate arrays (FPGAs) on NI reconfigurable I/O (RIO) hardware.
Message Edited by My NI on 08-13-2009 10:07 AM
Regards
MY

Calling 2 FPGA in Real-Time VI

Im using an sbRIO and I have 2 FPGA in it. I program both to open in real time. FPGA 1 is regarding getting data from analog signal and FPGA 2 is sending PWM. If these 2 are seperated, I have no problem opening them in real time. When I combine them together in a single real time VI, only FPGA 2 is working. FPGA 1, which supposedly shows values in charts is just totally empty!
Question is, how do I integrate both FPGAs in a single real time VI? Will combining the codes in FPGA screw up the timing?

I'm pretty sure the sbRIO cards only have 1 FPGA on them. So when you load the second FPGA code, the first is being overwritten. You need to make a single FPGA VI that can handle both functions. If you post your code, we can give more detailed advice.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines

How can I install (download) a Labview FPGA code onto Altera FPGA chip using Labview FPGA module?

Hi there
Guys i'm a very new labview user (PhD student), my project is about ( design and implementation of a high speed-yet sophisticated system using Labview environment then install this project's code (using Labview FPGA module) onto Altera-made FPGA chip).
so kindly, can any body help me in this?...is there any way to connect labview with Altera FPGA?...please anything would be said 'd be of great benifits
thanks a lot in advance.

as previously mentioned, labview fpga only supports national instruments targets utilizing xilinx fpgas. the hdl generated by labview fpga is encrypted and cannot be used to synthesize a design outside the labview fpga design flow.
however, if you must use labview for your project, it might be possible for you to design the system in labview and use one of the labview embedded modules ( http://www.ni.com/embedded )to generate c code which you can then port to systemc and compile for the altera fpga. i'm not saying it will be easy, but it should be possible.

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
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Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Creating multiple tasks in labview fpga

Hi,
I need to create multiple tasks in labview fpga....I need to set one update period in each task so that i can make my while loop run at this rate everytime my input frequency changes....How do i do this?

Hi,
just to be sure: You are talking about multiple tasks on the FPGA to acquire data? Or do you want to have multiple tasks on the host to display the data?

LabVIEW FPGA driver for Xilinx SPARTAN 3E Starter Board

i need drivers for spartan 3E .

If you are at a university that has a site license for the FPGA module, the following might be of interest to you:
Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUP Starter Kit
See also this discussion.
Quote from the license agreement:
...INSTALLATION AND USE OF THE LABVIEW FPGA TARGET MODULE FOR THE XILINX SPARTAN-3E STARTER BOARD (THE “TARGET MODULE”) IS LIMITED TO ACADEMIC INSTITUTIONS THAT HAVE A VALID, CURRENT “ACADEMIC TEACHING LICENSE” FROM NATIONAL INSTRUMENTS FOR THE LABVIEW FPGA MODULE. THIS TARGET MODULE MAY ONLY BE USED FOR INSTRUCTIONAL PURPOSES, SUBJECT TO THE TERMS AND CONDITIONS OF THE NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT THAT ACCOMPANIES THE SOFTWARE...
LabVIEW Champion . Do more with less code and in less time .

Labview fpga vs xilinx ise

hi all
i am new to fpga and my question is fairly simple one which one is better ?
labview fpga or the xilinx ise platform ?
or does it depend upon the application?
Regards
Solved!
Go to Solution.

It always depends on the application. Better in what way?
I like programming in LabVIEW, so I think LabVIEW FPGA is a much better choice. Learn just a little more than regular LabVIEW and you can program an FPGA! Unless you have experience using ise, I suspect LabVIEW would be the easier route.
If you are looking at price, maybe ise wins. It isn't cheap to get buy LabVIEW and the FPGA module (and probably RT module) so you have all the tools.
If the task is very complex, you might manage to make the program slightly more efficient using a lower level tool like ise. You might shave off a few nanoseconds of loop time. In 99.9% of the cases, this is unlikely. LabVIEW code does a pretty good job converting over to FPGA.
Bruce
Bruce Ammons
Ammons Engineering

Labview FPGA for beginners.

Hello.
I have no idea what labview is and how to work with this. I have had some experience with Xilinx 12.1 EDK (microblaze and VHDL).
I tried to install labview and labview fpga module. It asked for some drivers and I continued, the program said that it will ask for the drivers later.
But, beside that, do you have any training flow to suggest? Should I start with labview or is it not necessary? After that, should I start with CVI or FPGA? I am confused. Any help is welcomed!
Thanks,
Bill.

See this video's to get start with labVIEW and more video's you can find in youtube. Also, get in touch with forum especially about FPGA questions or read the history question targeting to your design area.
http://zone.ni.com/devzone/cda/tut/p/id/7466
I never use FPGA codes or concepts in labVIEW but I am looking to learn now.

Labview fpga module 8.6

I want use labview FPGA modul 8.6 can somebody help me to dowlaond this modul thanks

Hi scream,
It would best contact your account representative within National Instruments, they will be able to determine how to best deliver this module to you. Thanks!
Matt S.
Industrial Communications Product Support Engineer
National Instruments

Labview FPGA called another software component

Hi
I am trying to compile my FPGA code which has previously compiled. I get this error.
"Labview FPGA called another software component, and that component returned the following error:
Error Code: -52009
NI Platform Services: The requested resource has been marked for deletion and is rejecting new requests."
What is this error code?

Hi,
I've been looking in to this for you today - unfortunately, that seems to be a really rare error code which doesn't come up very often on our systems, so there's no quick fix that I can find.
A couple of options:
1) Have you made any changes to the code recently, in terms of updating it from an earlier version of LabVIEW? If so, it may be worth mass compiling your project up to the latest version in case there are references to software components which no longer exist.
2) It's probably worth a try repairing your LabVIEW, FPGA and RIO drivers installations from disk, as described here: http://digital.ni.com/public.nsf/allkb/FE6B641E86E55AF2862576DE00038001?OpenDocument
This could be due to some kind of missing or corrupted component in, for example, the Xilinx Tools
3) Are you referencing any kind of external software, such as DLLs or third party instruments, in your file?
4) What hardware are you using?
Please let me know how you get on with these queries.
Best wishes,
Chiara A
Applications Engineer with NI UK & Ireland

Qual a diferença do LabVIEW FPGA e o LabVIEW REAL- TIME?

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