Query Panel Greyed Out

I need to access the Query Panel to define a prompt and filter that the user will fill out before the report is generated. The Query Panel is grayed out. Where do you assign rights for users? I am the admin of this machine.

After CR 9 you no longer have the option to edit the SQL statement. Use a Command object.

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    Phil Dx wrote:
    <deleted>
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    AVX             -       Supports AVX intruction extensions
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    MTRR            *       Supports Memory Type Range Registers
    XSAVE           -       Supports XSAVE/XRSTOR instructions
    OSXSAVE         -       Supports XSETBV/XGETBV instructions
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    MOVBE           -       Supports MOVBE instruction
    PCLULDQ         -       Supports PCLMULDQ instruction
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    SEP             *       Supports fast system call instructions
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    Copyright (C) 2008-2012 Mark Russinovich
    Sysinternals - www.sysinternals.com
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    Intel64 Family 6 Model 58 Stepping 9, GenuineIntel
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    HYPERVISOR      -       Hypervisor is present
    VMX             *       Supports Intel hardware-assisted virtualization
    SVM             -       Supports AMD hardware-assisted virtualization
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    SMX             -       Supports Intel trusted execution
    SKINIT          -       Supports AMD SKINIT
    NX              *       Supports no-execute page protection
    SMEP            *       Supports Supervisor Mode Execution Prevention
    SMAP            -       Supports Supervisor Mode Access Prevention
    PAGE1GB         -       Supports 1 GB large pages
    PAE             *       Supports > 32-bit physical addresses
    PAT             *       Supports Page Attribute Table
    PSE             *       Supports 4 MB pages
    PSE36           *       Supports > 32-bit address 4 MB pages
    PGE             *       Supports global bit in page tables
    SS              *       Supports bus snooping for cache operations
    VME             *       Supports Virtual-8086 mode
    RDWRFSGSBASE    *       Supports direct GS/FS base access
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    MMX             *       Supports MMX instruction set
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    3DNOWEXT        -       Supports 3DNow! extension instructions
    SSE             *       Supports Streaming SIMD Extensions
    SSE2            *       Supports Streaming SIMD Extensions 2
    SSE3            *       Supports Streaming SIMD Extensions 3
    SSSE3           *       Supports Supplemental SIMD Extensions 3
    SSE4.1          *       Supports Streaming SIMD Extensions 4.1
    SSE4.2          *       Supports Streaming SIMD Extensions 4.2
    AES             *       Supports AES extensions
    AVX             *       Supports AVX intruction extensions
    FMA             -       Supports FMA extensions using YMM state
    MSR             *       Implements RDMSR/WRMSR instructions
    MTRR            *       Supports Memory Type Range Registers
    XSAVE           *       Supports XSAVE/XRSTOR instructions
    OSXSAVE         *       Supports XSETBV/XGETBV instructions
    RDRAND          *       Supports RDRAND instruction
    RDSEED          -       Supports RDSEED instruction
    CMOV            *       Supports CMOVcc instruction
    CLFSH           *       Supports CLFLUSH instruction
    CX8             *       Supports compare and exchange 8-byte instructions
    CX16            *       Supports CMPXCHG16B instruction
    BMI1            -       Supports bit manipulation extensions 1
    BMI2            -       Supports bit maniuplation extensions 2
    ADX             -       Supports ADCX/ADOX instructions
    DCA             -       Supports prefetch from memory-mapped device
    F16C            *       Supports half-precision instruction
    FXSR            *       Supports FXSAVE/FXSTOR instructions
    FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
    MONITOR         *       Supports MONITOR and MWAIT instructions
    MOVBE           -       Supports MOVBE instruction
    ERMSB           *       Supports Enhanced REP MOVSB/STOSB
    PCLULDQ         *       Supports PCLMULDQ instruction
    POPCNT          *       Supports POPCNT instruction
    SEP             *       Supports fast system call instructions
    LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
    HLE             -       Supports Hardware Lock Elision instructions
    RTM             -       Supports Restricted Transactional Memory instructions
    DE              *       Supports I/O breakpoints including CR4.DE
    DTES64          *       Can write history of 64-bit branch addresses
    DS              *       Implements memory-resident debug buffer
    DS-CPL          *       Supports Debug Store feature with CPL
    PCID            *       Supports PCIDs and settable CR4.PCIDE
    INVPCID         -       Supports INVPCID instruction
    PDCM            *       Supports Performance Capabilities MSR
    RDTSCP          *       Supports RDTSCP instruction
    TSC             *       Supports RDTSC instruction
    TSC-DEADLINE    *       Local APIC supports one-shot deadline timer
    TSC-INVARIANT   *       TSC runs at constant rate
    xTPR            *       Supports disabling task priority messages
    EIST            *       Supports Enhanced Intel Speedstep
    ACPI            *       Implements MSR for power management
    TM              *       Implements thermal monitor circuitry
    TM2             *       Implements Thermal Monitor 2 control
    APIC            *       Implements software-accessible local APIC
    x2APIC          *       Supports x2APIC
    CNXT-ID         -       L1 data cache mode adaptive or BIOS
    MCE             *       Supports Machine Check, INT18 and CR4.MCE
    MCA             *       Implements Machine Check Architecture
    PBE             *       Supports use of FERR#/PBE# pin
    PSN             -       Implements 96-bit processor serial number
    PREFETCHW       *       Supports PREFETCHW instruction
    Logical to Physical Processor Map:
    **--  Physical Processor 0 (Hyperthreaded)
    --**  Physical Processor 1 (Hyperthreaded)
    Logical Processor to Socket Map:
    ****  Socket 0
    Logical Processor to NUMA Node Map:
    ****  NUMA Node 0
    Logical Processor to Cache Map:
    **--  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
    **--  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
    **--  Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
    ****  Unified Cache       1, Level 3,    4 MB, Assoc  16, LineSize  64
    --**  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
    --**  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
    --**  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64
    Logical Processor to Group Map:
    ****  Group 0

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