Readback example for virtex 7 family
Hi All,
I am new to Xilinx Vivado tool. I am looking forward to create a simple example in Vivado for Virtex 7 to test out the readback capture and readback verify capability .
Can I get some working example which I can directly run on my board and test out the readback feature? Or any documentation giving details on implementation would help.
Rgds
Sapan
Thanks Vijay. This information will be very handy. Just wanted to know if we need to instantaite any Xilinx Readback primitive in our design to enable readback? Or just the command sequence would work?
And if I am right , the documentation covers, readback verify only. Is there anything specific needed for readback capture ?
Rgds
Sapan
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