REG: Simulation of FM 'Posting_Inetrface_ocument'

Hi,
Is there any procedure to simulate the function module POSTING_INTERFACE_DOCUMENT. When this is executed it should check whether a document gets posted successfully but should NOT create a document.
Regards,
Bhanu

HI syd,
I think, there's no fm.
the only possibility i see is to make
a call transaction of fb01 in mode 'E'
with fcode BS (=simulate)
and finally RW (=back)
And than analyse errortab, which you get back from call TA.
regards Andreas

Similar Messages

Reg:Simulation version key issue

Hi,
I am using simulation version key as SIM+++ .But as per document given below:-
The valid version numbers for simulation version can be entered in Customizing.
You can use the formatting characters + and *:
+ means exactly one character
If you enter SIM+++ the maximum length of the version number is restricted to 6 characters.
is a character string of no defined length at the end of the version number (up to the maximum length of 12 characters).*
If version numbers for simulations have been entered in Customizing, then you can only create versions that correspond with one of these entries
but when i am creating Simulation version SIMAA3 then also system is accepting whereas as per above document + sign is for character and not for digit.
So Kindly guide me in resolving this issue.
With Regards
Rohit Prakash

Project Version is snapshot/photo of project, you cant change it. It is generally taken to record the exact project status at that point of time.
Simulation version is used to simulate 'if then' conditions.Generally used during quotation phase or if you want see effect of particular event on project you can create simulation version see the effect and transfer back to operative or delete.
Project Version is only for info purpose and cant be transfered anywhere. Simulation version can be transfered to operative project.
1. http://help.sap.com/saphelp_erp60_sp/helpdata/en/d8/1fe8344d1d166be10000009b38f83b/frameset.htm
2. http://help.sap.com/saphelp_erp60_sp/helpdata/en/0b/ba853488601e33e10000009b38f83b/frameset.htm
Regards

Reg : Simulation in FB01

Hi,
We have Custom program to post the document in FB01 using BDC.User asked us to show the data in ALV before posting the document like simulation in FB01. We have documents in the internal table before passing the data into BDC program.?
Is it possible to simulate the document like in FB01 Simulation.? Is it there any function module to simulate the FI doucuments.?
Thanks in Adavance
P.Senthil Kumar

Hi Thomas,
Is this function module(BAPI_ACC_DOCUMENT_CHECK) act like simulation in FB01.My requirement is that in selection screen, i want to add "Test Run Only" option,If user selected this one then i want to show the required details for posting and simulation of posting data but actual posting should not happen when i executing this program with test run.
Actually this custom program already created by some one which has BDC program to post the document.so i need to add one option test run.
Layout should be display the following fields (Layout data should have both credit and debit entries)
Documnet Number   (test Run)
Reference             BKPF-XBLNR
Company Code     BSEG-BUKRS
Item             BSEG-BUZEI
Currency             BKPF-WAERS
Posting key             BSEG-BSCHL
Account             BSEG-HKONT
Amount              BSEG-WRBTR
Material             BSEG-MATNR
Quantity             BSEG-MENGE
Trading Partner     BSEG-VBUND
Cost Centre             BSEG-KOSTL
Profit Center            BSEG-PRCTR
Functional Area   BSEG-FKBER
Sales order         BSEG-VBEL2
Regards
P.Senthil Kumar
Edited by: senthil kumar on Mar 11, 2010 12:02 PM
Edited by: senthil kumar on Mar 11, 2010 12:03 PM
Edited by: senthil kumar on Mar 11, 2010 2:19 PM

Reg.Simulation entry missing from configuration

Dear Experts
I am newly configure in IDES system,in which I create Inventory A/c,Consumption account,GR/IR a/c,Inv offsetting a/c,Inc/Dec a/c,Cash payable on purchase a/c ,Gain loss revaluation a/c and Loss in exchange rate a/c and configured in OBYC ,but in OMWB->Simulation all assigned are missing -
Posting line text PK Acct Deb PK Acct.Cr
Inventory Posting 83 Missing 93 Missing
Pls help me where I have missed to assign the G/L Account.And how to configure for come in OMWB settings.
Thanks
Rajakumar.K

Please maintain GL Codes against Gen Modifier/Valuation Class in OBYC settings.
Regards,
Alok

Reg:Operative and simulation version comparison in cn41

Hi,
I am doing comparison of date between Operative project and Simulation project(cn41) .But all the object are displaying row wise in single column
Project Object                                      Ear Start                        Ear Finish
Activity1(operative)                                  11.03.2011                        16.03.2011
Activity1(Simulation)                                 20.03.2011                       15.03.2011
But I want it to display like this(Both operative and simulation separately)
Project Object       Ear Start(Op)          Ear Finish(Op) Ear Start(Si)         Ear Finish(Si)
Activity1(operative)
Activity1(Simulation)
How it can be possible.Can Any body give some idea and way to resolve this issue.
With Regards
Rohit Prakash
Edited by: rohitSAPCOMMUNITY on Mar 15, 2011 6:16 AM

hi sophie,
create separate network for each wbs in project. see if this can solve your issue.
vengaiah chowdary

Reg. No G/L account assign in simulation entry

Dear Experts
I configured Account assignment,After that I checked in OMWB -Simulation ,the PK Acct.Dr and PK Acct Cr. is missing for all account like inventory,Gain/Loss etc..
Where I have missed to assign the G/L account fo come in OMWB Simulation check. Pls advise as soon as possible
In OBYC I configured all required accounts. then where to assign too.
Thanks
Rajakumar.

I have maintained BSX,GBB and WRX ,even these doesn't assign in PK Acct DR and PK Acct CR.
Pls advise at the earliest.
Thanks
Rajakumar.K

Need of ARINC 429 Simulator-reg

Hi,
what is the need of ARINC 429 simulator? What does it will do
whether encode or decode?
Please give me detaied information in this regard if anyone knows
about it so that i'll be thankful to you.
Thanks and regards
K. Bhogasena reddy

I'm not sure quite what your after but there's a Arinc 429 tutorial here:
http://www.aim-online.com/databus_tutorials.aspx
it may help you.
Ian

Reg. FI entry in OMWB - Simulation entry

Dear Experts
I have configured newly in IDES system for Account determination. And saw my configuration in IDES OMWB like the below
Plant           1001    -> Company Code    NCCP -> Chart of Accounts    NCCA
                              -> Valuation Area     1001 -> Valuation Grpg Code 1000
Material         DYEDCTNLACE                    -> Valuation Class      9101
                                                                     Material Type   ACCE ->
Movement Type    101       GR goods receipt
Posting Lines Text                    VlGCd   AGC   VCl     PK       Acct Deb.         PK      Acct Cr.
Gain/loss from revaluation         1000                9101    83     --Missing-            93      --Missing-
Inventory posting                        -e-         -e-     9101    89     --Missing-            99     --Missing-
Incidental costs of external a     1000        -e-    9101     86     --Missing-            96     --Missing-
External activity                        1000        -e-    9101    86      --Missing-            96     --Missing-
Change in stock account           1000        -e-    9101    81      --Missing-            91    --Missing-
Purchase offsetting account       1000        -e-    9101    40      --Missing-            50    --Missing-
Purchase account                     1000        -e-    9101    40      --Missing-            50    --Missing-
Materials management exch.rate1000                9101    83     --Missing-             93    --Missing-
Cost (price) differences              1000                9101    86     --Missing-             96    --Missing-
GR/IR clearing account               -e-          -e-     9101    86    --Missing-             96    --Missing-
Inventory posting                        -e-          -e-     9101    89    --Missing-
But I have configured Stock account(BSX),consumption accountGBB-VBR,VBO,VBK,ZOB,ZBO,VAX AND ZOF, GR/IR account WRX.Cash payable in purchase account,Inc/Dec account,Inv offsetting account.
And where to assign these account to fill the above missing. For Example,ref below that I took from our development.
                                                                                Plant           1001 -> Company Code    NCCP -> Chart of Accounts    NCCA
                       -> Valuation area 1001 -> Valuation Grpg Code 1000
Material         BUTTTERFLY-N                   -> Valuation Class      9116
                                                                    Material Type        ACCE ->
Movement Type    101       GR goods receipt
Posting Lines Text                         VlGCd        AGC      VCl      PK     Acct D      PK      Acct Cr
Gain/loss from revaluation                  -e-            -e-         -e-       83     313003      93       313003
Inventory posting                               -e-            -e-        9116     89     221616      99       221616
Incidental costs of external a            1000           -e-        9116     86   --Missing-    96     --Missing-
External activity                                 -e-            -e-        9116     86   --Missing-    96     --Missing-
Change in stock account                    -e-            -e-        9116     81   --Missing-    91     --Missing-
Purchase offsetting account                -e-            -e-          -e-      40   --Missing-    50     --Missing-
Purchase account                              -e-            -e-          -e-      40    --Missing-   50     --Missing-
Materials management exch.rate         -e-            -e-          -e-      83      491103    93       313002
Cost (price) differences                       -e-            -e-                    86      313003    96       313003
GR/IR clearing account                       -e-            -e-        9116     86      504020    96       504020
Inventory posting                                 -e-            -e-       9116      89      221616
Pls help immediately
Thansk
Rajakumar.K

Please maintain GL Codes against Gen Modifier/Valuation Class in OBYC settings.
Regards,
Alok

Reg:Notes for simulation to operative

Hi,
I am getting run time error during Version---->operative data transfer...Can anybody suggests some of the notes applicable for it.
These are the details:-
Runtime Errors                    SAPSQL_INVALID_FIELDNAME
Except.                    CX_SY_DYNAMIC_OSQL_SEMANTICS
Date and Time                    16.05.2011     17:08:18
*What happened?                         *
*     Error in the ABAP Application Program                    *
*     The current ABAP program "SAPLCOLA" had to be terminated because it has                    *
*     come across a statement that unfortunately cannot be executed.                    *
*Error analysis                         *
*     An exception occurred that is explained in detail below.                    *
*     The exception, which is assigned to class 'CX_SY_DYNAMIC_OSQL_SEMANTICS', was                    *
*      not caught in                    *
*     procedure "CO_LA_OPER_SEQ_PRE_READ_DB_VER" "(FUNCTION)", nor was it propagated                    *
*      by a RAISING clause.                    *
*     Since the caller of the procedure could not have anticipated that the                    *
*     exception would occur, the current program is terminated.                    *
*     The reason for the exception is:                    *
*     An Open SQL clause was specified dynamically. The contained field name                    *
*     TPLNR does not exist in any of the database tables from the FROM clause.     *
With Regards
Rohit

Dear Rohit,
Please find the Note 1319565 - Dump in transaction CJV4.
Ask your abaper to append a field to the table VSAFVC_CN. Please check the note for more details.
Best Regards,
Punith.

HELP REG Java NEtwork Simulator

HI,
This is Ashwin from India.
I need some tutorials and examples regarding jns...kindly help me by sending their links...

Ashwintk wrote:
I HAV DOWNLOADED JNS.....
BT DON'T KNOW WER 2 START.....HOW 2 START....
SO PLS HELP!!!!!You really expect free support on every single product ever written in Java? Good luck with that

How to show waveform in Vivado simulation window? The waveform is absent for some signals.

Hi,
I have the following verilog code:
`timescale 1ns / 1ps
module top(
reg clk = 1;
always
#1.25 clk <= ~clk;
wire temp;
//wire temp2; // added later
assign temp = clk;
//assign temp2 = clk; //added later
endmodule
When I simulate this, I see "CLK" as expected but "temp" just has the value 1 and no waveform. When I uncomment the lines marked as "//added later", I can see "CLK" and "temp2" waveforms as expected. But "temp" is still stuck at 1 and there's not waveform for it.
Then I commented the lines marked as "//added later" again and there's not waveform for "temp". Then I renamed "temp" to "temp2" and simulated. This time I could see "CLK" and "temp2" waveforms in the simulation window toggling as expected.
It could be that I'm just not seeing the waveforms. For example in the first scenario, I'm just seeing a "1" and no waveform. There are also some other signals that when added to the wave window don't show a waveform. How can I enable the waveform?
Thanks,

I tried using a separate module for clock generation as you suggested. In my top level module I instantiate two clocks "CLK_20MHz" and "CLK_25MHz". When I simulate I can see the waveform of both clocks. Then, from the clock module, I add the register "CLK". However, I see no waveforms for "CLK". But when I add "$monitor("%d,\t%b",$time, CLK);" inside the clock module, I can see in the logs that "CLK" is actually toggling as expected. I don't know why the simulation window doesn't show the waveform? And how I can show/enable the waveform?

Sytem Generator generated IP simulation mismatch

Hi,
I am using Vivado 2014.2 & SystemGenerator 2014.2
To demonstrate the problem I have made a simple register using System Generator MCode block. Converted that in to an IP to be used in Vivado IP Integrator.
I insert my simple register IP, generate an HDL wrapper and with a testbench I simulate it.
The problem is that there is a mismatch between the Behavioral simulation and the post-synthesis. The behavioral simulation result shows that no register is infered where as post-synthesis simulation seems correct. Results are shown below.
Could this be a bug? or am I missing something.
I am also attaching files needed to reproduce the problem.
Regards

yes post synthesis simulation seems correct. Can you generate the RTL and see if it infer reg correctly

Simple Project Simulation Example

Lets Consider a simple full adder project:
`timescale 1ns / 1ps
module add(var1,var2,add,clk,cin,cout);
input [3:0] var1;
input [3:0] var2;
output reg [3:0] add;
input clk;
input cin;
output reg cout;
always @ (posedge clk) begin
{cout,add}=var1+var2+cin;
end
endmodule
This this the adder module
`timescale 1ns / 1ps
module top();
reg [3:0] var1;
reg [3:0] var2;
wire [3:0] add;
reg cin;
wire cout;
reg clk=0;
add A1(.cin(cin),.cout(cout),.add(add),.var1(var1),.var2(var2),.clk(clk));
initial begin
var1=3;
var2=2;
cin=1;
end
initial #2 $finish;
initial begin
forever
#1 clk=~clk;
end
endmodule
This code is only used for simulation purpose.
Can anybody explain what mistake i am doing?
I have attached the snapshots for Behavioural simulation,Post synthesis functional Simulation and Post synthesis Timing Simulation.

HI,
When you create a test bench, remember that the GSR pulse occurs automatically in the post-synthesis and post-implementation simulation. This holds all registers in reset for the first 100 ns of the simulation.
As mentioned by muzaffer you are not waiting long enough to get out of the GSR condition.
Change the initial statemnet as below and you will be able to see the expected results.
initial #102 $finish;
For more details on GSR please refer to below user guide Global set and Reset section.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug900-vivado-logic-simulation.pdf
The following bullets are recommendations for creating an effective test bench.
• Always specify the `timescale in Verilog test bench files.
• Initialize all inputs to the design within the test bench at simulation time zero to properly begin simulation with known values.
• Apply stimulus data after 100ns to account for the default Global Set/Reset (GSR) pulse used in UNISIM and SIMPRIMS-based simulation.
• Begin the clock source before the Global Set/Reset (GSR) is released

Dep Simulation Distribution

Hi,
Internal order with Investment Management & Depreciation simulation data have multiple lines to enter asset class wise / cost center wise / capitalization date wise percentages or amount. System=R/3 4.6C
But client wants only one line to be available for entry with 100% as default.
Any help please.
Kind regards,
Naresh

Hello
In the settlement parameters, you need to assign a settlement profile to the internal order. As you cannot maintain settlement parameters when you settle to one receiver, you can store the settlement profile in the order type. Otherwise, you need to create the internal order with the help of a reference order, which has a settlement profile assigned to it.
Before you can settle an order, it must have a status that allows the Settlement business transaction. If you posted revenues to internal orders, you cannot settle them to cost centers.
In the settlement parameters, you need to assign a settlement profile to the internal order. As you cannot maintain settlement parameters when you settle to one receiver, you can store the settlement profile in the order type. Otherwise, you need to create the internal order with the help of a reference order, which has a settlement profile assigned to it.
Before you can settle an order, it must have a status that allows the Settlement business transaction. If you posted revenues to internal orders, you cannot settle them to cost centers.
Line item apportionment
You only require line item apportionment for capital-investment measures. You can find more information on line item apportionment for capital-investment measures in the SAP Library
also check Financials ® CO Controlling ® Internal Orders ® Settlement.
reg
*assign points if useful

About ISIM simulator and Test Bench with verilog, output .txt to Matlab

Software : ISE 14.3
Simulator : ISim by xilinx.
I am a beginner to learn the verilog and FPGA.
I want to use FPGA to process image. After processing, I require to read the processed data into Matlab for matching the results .
I have stored 256*256,8bit image into the ROM.
This is my module.
module image_top
input clka,
input ena,
input rst_n,
output [7:0] douta,
output reg rd_stop
reg[15:0]addra;
always@(posedge clka or negedge rst_n)
begin
if(!rst_n)
addra <= 0;
else if(ena)
addra <= addra + 1;
else
addra <= addra;
end
wire rd_stop_flag;
assign rd_stop_flag = (addra == 65535-1)?1:0;
//reg rd_stop;
always@(posedge clka or negedge rst_n)
begin
if(!rst_n)
rd_stop <= 0;
else if(rd_stop_flag)
rd_stop <= 1;
else
rd_stop <= rd_stop;
end
ImageMem u_imgemem
.clka (clka), // input clka
.ena (ena&&!rd_stop), // input ena
.addra (addra), // input [15 : 0] addra
.douta (douta) // output [7 : 0] douta
endmodule
This is my TestBench. I am not sure this is correct.
`timescale 1ns / 1ps
// Company:
// Engineer:
module TB_top;
// Inputs
reg clka;
reg ena;
reg rst_n;
// Outputs
wire [7:0] douta;
wire rd_stop;
// Instantiate the Unit Under Test (UUT)
image_top uut
.clka(clka),
.ena(ena),
.rst_n(rst_n),
.douta(douta),
.rd_stop(rd_stop)
integer fp_w,j;
initial
begin
// Initialize Inputs
clka = 0;
ena = 0;
rst_n = 0;
fp_w = $fopen("image_out.txt","w");
// Wait 100 ns for global reset to finish
#100 rst_n =1;
#20 ena = 1;
// Add stimulus here
for(j = 0; j < 65536; j= j+1)
begin
$fwrite(fp_w,"%d\n",douta);
end
$fclose(fp_w);
end
always #5 clka = ~clka;
endmodule
This is my TestBench.
After synthesis, In the project,there is a' image_out.txt' file,but the datas in it are all zero.
I wonder what is the problem?
This is my simulation waveform by ISIM.
I wonder if ISIM isn't good to support ''for-loop" or system command like $fwrite?
If true, I have to install the modelsim simulator.
Thank you for your reply!

The bug is in your testbench.
Inside the for loop, you haven't given any opportunity for time to advance. So, the entire 64K iterations of the loop happen "instantaneously" at the same moment in time. This means that there have been no clock periods inside the loop - you are effectively writing the same output of your design (which is 0) 64K times. Advancing time is necessary since your address counter only changes state once per clock period; so all the fwrite's of dout are getting the data from the same address location.
At very least you need to put an "@(posedge clk)" or at least a #10 inside your for loop to allow time to progress (so that you get the output of the module on different clock periods).
Avrum

REG: Simulation of FM 'Posting_Inetrface_ocument'

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