Register Map Wizard

Has anyone built a register map wizard for register type communication? Basically I'm looking to shorten my development time. I've built some register map user interfaces manually before but want to create a wizard that will dynamically create the map (number of registers and bit width). Thanks in advance for any help.

You might be interested in the NI Measurement Hardware Driver Development Kit (DDK). The Measurement Hardware DDK is a driver development kit containing development tools and register-level programming interface for NI measurement hardware. It offers a register-level programming interface as well as example programs to get you started quickly.
And best of all, it's a free download!! Enjoy.
Kileen C.
NI

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Access to Cisco Switch Modbus Register Map? via Modbus TCP or Modbus RTU

Hello Folks, I have been trying to find out how to access the Modbus Register Map(s) of Cisco switches, of particular interest is that of an IE 3000 as it is din rail mountable (but for models 2960s, 3560s are also of interest). A google search for: Cisco Switch Modbus TCP results in (if I may) how to configure a Cisco 2520 to do what I am trying to do. I would be very grateful for any hints anybody might have. Thanks

Though I am not familiar with the specific drives in question, I have used Modbus/TCP in LabVIEW a few times recently.
As the previous posters pointed out, there are a couple of VI libraries available. LabVIEW 2014 added Modbus VI's with the DSC and LabVIEW Real-Time. The others you would have to get and add in yourself.
Another option is to use LabVIEW I/O Servers; as long as you have DSC or Real-Time, you can create Modbus I/O Servers as library items and deploy to a target. You don't get as much direct control in this way (and may run into difficulties if you need them to be field-configurable and do not have DSC) and use bound network shared variables, but they are very fast and easy to setup and I have yet to have any issues with using them in my applications.
A tutorial on setting up a Modbus I/O Server: http://www.ni.com/tutorial/13911/en/
A tidbit on deciding between Modbus VI's and a Modbus I/O Server: http://zone.ni.com/reference/en-XX/help/370622M-01/lvmve/choose_modbus_ioserver_vi/
As for using an Ethernet switch to connect multiple devices, I have used this approach many times to simultaneously connect and control numerous PC's, real-time controllers, and drives without issue. I would not expect there to be any problems unless you have extenuating circumstances. In fact, if you only have one network interface on your device at the moment, I would recommend against adding a second, as this would mean that you / your controller would have to be extra aware of which interface everything is assigned to go through.

NI PCIE 6259 Register Map

I need to write a custom driver for this board. Does anyone know where I can get a regsiter map?

I had already downloaded DDK and found the Register Map document. At a minumum this is what I need but I thought the information was on the little light side. It would be nice to have some descriptions for the registers and their bit fields. Also, the "M Series Register Map" is a Preliminary document. Any idea when the next version will be available?
I did not find any information about board specific Register Maps so I assume that this map is good for all 'M' Series boards.
I was hoping to find something like the "PCI E Series Register-Level Programmer Manual" at: http://digital.ni.com/manuals.nsf/websearch/5978CE4A83119E50862566FA0075F424 .
Reading through the posts it seems that there is a lot of differences between the 'E' and 'M' series mulit-function DAQs so
Thank you for the reply.

PCI register mapping

Hi all,
I have a device as for which I am trying to do a IO_MAPPED driver.
I am doing on my Ultra60 the following code:
size_t memory_size;
for( i=0; i<6; i++ )
ddi_dev_regsize(dip, i, &memory_size);
result = ddi_regs_map_setup(dip, i,
&drx->ioBase.address, 0, mem_size,
&devAttr, &drx->ioBase.handle);
printf("ddi_regs_map_setup(,%d,,,0x%X,,)
returned %d\n", i, mem_size, result );
if (result == DDI_SUCCESS)
ddi_regs_map_free(&drx->ioBase.handle);
On the Ultra60, the reg sizes are:
ddi_regs_map_setup(,0,,,0x0,,) returned 0
ddi_regs_map_setup(,1,,,0x100,,) returned 0
ddi_regs_map_setup(,2,,,0x1000,,) returned -7
ddi_regs_map_setup(,3,,,0x100,,) returned 0
ddi_regs_map_setup(,4,,,0x1000,,) returned -7
ddi_regs_map_setup(,5,,,0x0,,) returned -6
My question is, if I want to map more than 0x200 sized device memory, how do i do it? Because rnumber 1 & 3 will allow me to map registers of sizes 0x100 each only!
or am i understanding this wrong?
any help appreciated!
Thanks!

Hi,
to be a bit more specific:
you shouldnt have to do any direct mapping of addresses yourself. both the register space, AND the io space of a PCI card should be accessible through
ddi_regs_map_setup.
If you download my PCIbase.tar from
http://www.bolthole.com/solaris/#drivers
it will give you a helper script called printregs,
which will show you which register set gets mapped to which address space.
It's always the same,for the same card. So if printregs says that the iospace memory you care about is in register set 3, then you can pretty much always use
ddi_regs_map_setup(dip, 3, ....) to map in that space.

Using other drivers' interrupt/register maps

2 related nasty low-level driver questions:
Lets say I wanted to have one driver handle hardware interrupts for another
driver that actualy binds to the hardware.
("bottom" == driver attached to hardware
"top" == driver that wants to hook into "bottom")
Is the best way to do that,
A) to have some kind of API in the "bottom" driver
that calls ddi_add_intr() directly registering a "top" function to call
B) to have some kind of API in the "bottom" driver
that calls ddi_add_intr() on its own function, which then calls
a registered function in the "top" module
C) ??
second related question: What about if I dont get to change the source code
in the "bottom" driver, but know it doesnt register an interrupt handler.
Is there a way for me to "steal" the interrupt in an efficient manner?
Is it as simple as the "top" driver figuring out the "dip" info for the
"bottom" driver, and calling ddi_add_intr() for itself?
Can I also use ddi_regs_map_setup with the other driver's dip information?
[oops, thats a third question :-)]

Thanks for the reply Doug.
I came to know that in websphere , there is "Last participant support" which allows exactly one NON XA with other XAs to participate in a transaction.
I am trying to do that.
I am using wsad 5.1.2, I dont know how to configure the server...

Complete E-series register map bitfield

I need to know (and use) ALL the STC register of my PCI-6014E board.I read all the forum.I downloaded all DDK documentation (RLPM and STC manuals).But there is not a complete description with bitfields of all registers in any place.I found only something (with no description) in the tSTC.h header file.
Can i find the complete bitfield description of all registers for PCI-6014E board from National or maybe i have to search other days on internet ???
Naturally my National dealer told me that all the support is in the National internet site...

Hello Studio,
Could you provide a bit more information about your application. Knowing more about what it is that you are trying to have the board do, will help us in providing you more specific information about the STC and other components of the board.
Christian L
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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6025E Register Map: where are the 82C55 Ports?

Hi,
I have written a driver for 6024E, and now would like to add support for the additional I/O ports available on 6025E. However, I can't seem to figure out the address to access these ports, and don't see any reference to these within the DDK files.
Any help would be appreciated -- thanks!
scott gillespie
applied brain, inc.

ok, I finally found this in comedi driver source:
#define Port_A 0x19
#define Port_B 0x1b
#define Port_C 0x1d
#define Configuration 0x1f
It must be in the NI docs somewhere, but for the life of me I can't find it.
scott gillespie
applied brain, inc.

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I'm using APEX 4.0.1 in a 10.2.0.4 database running on Windows.
Any thoughts?

Hi mjblake,
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Regards,
Hilary

How to register user in Warehouse Builder

Hi All,
I have installed OWB 11g in my machine. I have created repository owner user in OLAP schema. In my process flows few flows are related to "OLAP instance" and few flows are related to "OLTP instance". Now I want to register my OLTP user present in OLTP instance, but when I start the wizard for registering user I get only OLAP instance users.
Please let me know how can I register my OLTP user of OLTP instance.
Is there any way to register database user manually in warehouse builder i.e. without using register user wizard?
Thanks
VishalS

Hi,
create the users as repos-owner in the design center or grant the roles to an existing db user. Don't make them to TARGET users!
Then selct the project, right mouse-click opens the context menue, select configuration, select the security tab and revoke all permissions except read from this users.
Regards,
Detlef

ANN: Eclipse EJB 3.0 Object-Relational Mapping Project Requirements posted

A document that presents an intitial feature and use case list for the early milestones of the Eclipse EJB 3.0 Object/Relational Mapping project has been posted to the project newsgroup (news://news.eclipse.org/eclipse.technology.ejb-orm). It also demonstrates a set of user interface components for editing EJB 3.0 Entities. The document covers the basics and is designed to illustrate the concept. It is in no way comprehensive. For example, it doesn't thoroughly cover the editing of ORM xml descriptors although this is an important requirement for the project. ORM xml support will be detailed in coming revisions, and slated for future milestones.
The purpose of this document is to invite comment on the approach. If you are interested in EJB 3.0 Entity support in Eclipse please give the doc a look over and post your feedback to the EJB 3.0 Object-Relational Mapping Project newsgroup.
Newsgroup: news://news.eclipse.org/eclipse.technology.ejb-orm
Simple Web Interface http://www.eclipse.org/newsportal/thread.php?group=eclipse.technology.ejb-orm
--Shaun Smith
Project Overview:
The goal of this project is to add comprehensive support to the Eclipse Project for the definition and editing of Object-Relational (O/R) mappings for EJB 3.0 Entity Beans. EJB 3.0 O/R mapping support will focus on minimizing the complexity of mapping by providing creation and automated initial mapping wizards, and programming assistance such as dynamic problem identification. The implementation will be extensible so third party vendors can add to its functionality.
Project Proposal:
http://www.eclipse.org/proposals/eclipse-ejb30-orm/index.html

A document that presents an intitial feature and use case list for the early milestones of the Eclipse EJB 3.0 Object/Relational Mapping project has been posted to the project newsgroup (news://news.eclipse.org/eclipse.technology.ejb-orm). It also demonstrates a set of user interface components for editing EJB 3.0 Entities. The document covers the basics and is designed to illustrate the concept. It is in no way comprehensive. For example, it doesn't thoroughly cover the editing of ORM xml descriptors although this is an important requirement for the project. ORM xml support will be detailed in coming revisions, and slated for future milestones.
The purpose of this document is to invite comment on the approach. If you are interested in EJB 3.0 Entity support in Eclipse please give the doc a look over and post your feedback to the EJB 3.0 Object-Relational Mapping Project newsgroup.
Newsgroup: news://news.eclipse.org/eclipse.technology.ejb-orm
Simple Web Interface http://www.eclipse.org/newsportal/thread.php?group=eclipse.technology.ejb-orm
--Shaun Smith
Project Overview:
The goal of this project is to add comprehensive support to the Eclipse Project for the definition and editing of Object-Relational (O/R) mappings for EJB 3.0 Entity Beans. EJB 3.0 O/R mapping support will focus on minimizing the complexity of mapping by providing creation and automated initial mapping wizards, and programming assistance such as dynamic problem identification. The implementation will be extensible so third party vendors can add to its functionality.
Project Proposal:
http://www.eclipse.org/proposals/eclipse-ejb30-orm/index.html

MAP Toolkit inventory computers on remote domain through vpn

Evening,
Basically as the title says I need to pull inventory report using MAP toolkit from my remote domains the access of which is achieved through VPN.
When I run the MAP wizard I get to the point were it asks me to specify domain (ex domainname.microsoft) and credentials. Is there any way to make like a domain connection on my computer to another domain or specify vpnip:MAPdomainspecificport instead.
Of course would that subsequently mean I'll then specify domainuser@vpnip:domainservicesport?
Long shot I know, just thought I'd try just in case.
Thanks

Although MAP uses WMI which relies on an RPC/DCOM protocol and PING uses ICMP, which is not the same, they both use DNS to resolve host names to IPs. If you can PING a machine using its host name from the MAP machine, then MAP should also be able
to route to it.
Please remember to click "Mark as Answer" on the post that helps you, and to click
"Unmark as Answer" if a marked post does not actually answer your question. Please
VOTE as HELPFUL if the post helps you. This can be beneficial to other community members reading the thread.

Problems configuring a port in niPXI-6509 card as input port using static DIO Register Level Programmer maual

Hello ,
I am using a ni PXI-6509 card for my application. Since I have to compile my application in Interval Zero RTX, I am using the static DIO Register level programming using VISA. I have successfully configured the card to do output on port0. But when I attempt to comfigure another port1(not the same as output) I can successflly configure it. But when I send 5V through the corresponding pins I donot get a value 1 in the Data register for that channel.
the following i did to configure as Input...
1) IO Select register set to 0 (for input as the manual suggests)
2) read from IO data register.
Do I need to do anything special to configure as input port.
please suggest...
Thanks
Kuchi

Hi Sathish,
Given how much blatant, undisclosed, and unrepentant
cross-posting [1] [2] [3] [4] [5] you've done to ask this question, I
gave you the benefit of the doubt that you were new to the NI forums
and didn't understand the etiquette of this community. However, looking
at your profile, you've been around just over 8 years! How can you be
so selfishly impolite?
To your credit, you at least searched the forums to find (somewhat) relevant to which topics to reply, but as you said you 'tried the entire NI Site', I'm surprised that you missed the DDK home page [6] that has a link to the M Series register map.
[1] Re: m series register programming in straight C
http://forums.ni.com/ni/board/message?board.id=90&message.id=1644#M1644
[2] Re: Problems configuring a port in niPXI-6509 card as input port using static DIO Register Level Programmer maual
http://forums.ni.com/ni/board/message?board.id=90&message.id=1645#M1645
[3] Re: Problem with writing to registers
http://forums.ni.com/ni/board/message?board.id=90&message.id=1646#M1646
[4] Re: Is there a Register Level Programming manual for NI 625x PXI
http://forums.ni.com/ni/board/message?board.id=270&message.id=7661#M7661
[5] Re: Where Can I find information about register level programming the PXI 6259?
http://forums.ni.com/ni/board/message?board.id=250&message.id=53551#M53551
[6] Register Level Programming for OEM Customers
http://digital.ni.com/express.nsf/bycode/exyv4w?opendocument
Joe Friedchicken
NI VirtualBench Application Software
Get with your fellow hardware users :: [ NI's VirtualBench User Group ]
Get with your fellow OS users :: [ NI's Linux User Group ] [ NI's OS X User Group ]
Get with your fellow developers :: [ NI's DAQmx Base User Group ] [ NI's DDK User Group ]
Senior Software Engineer :: Multifunction Instruments Applications Group
Software Engineer :: Measurements RLP Group (until Mar 2014)
Applications Engineer :: High Speed Product Group (until Sep 2008)

Register level programming of interrupts for PCI 6503

Hi all,
I'm basically trying to get an interrupt from the card upon a change in the data of one of the ports (for instance port A) so I can catch pulse signals without having to poll the pins manually at a high rate. I can't figure out from the documentation and examples whether this is actually possible using register level programming (can't use the DAQmX libraries because I use InTime OS). I can set the appropriate bits of the Interrupt Registers in order to enable the two interrupts (A and B), but I'm not sure what condition generates these interrupts.
Additionally, I want to be able to send out a pulse on a pin and have it automatically cleared by the board.
As far as I can tell both of my requirements mean using the card in strobed mode, but the code examples don't give enough information how to work in this mode. Do i have to use the handshaking mechanism somehow and if so, how is this better for me over using static i/o and manually checking pin values?
Any help or referrence would be greatly appreciated.
Thank you in advance
Orr

Hi Orr,
The best source of information for this device is its user manual [1], and Appendix B discusses the register map and programming considerations.
Speaking specifically to interrupts, please refer to PDF page 43 (B-2), emphasis mine:
Two software-controlled registers determine which devices, if any, generate interrupts. Each of the 82C55A devices has two interrupt lines, PC3 and PC0, connected to the interrupt circuitry. On the PCI-DIO-96 and PXI-6508, the 82C53 device has two of its three counter outputs connected to the interrupt circuitry. Any of these 10 signals can interrupt the computer if the interrupt circuitry is enabled and the corresponding enable bit is set. Refer to the Programming Considerations for the 82C53 section for more information. Normally, the handshaking circuitry controls PC3 and PC0 of the 82C55A devices; however, you can configure either of these two lines for input and then use them as external interrupts. An interrupt occurs on the signal line low-to-high transition."
The pages following that section describe the interrupt control registers and give pseudo-code examples for configuring them.
Once we clear this obstacle, let's move on to your output questions.
[1] PCI-DIO-96/PXI-6508/PCI-6503 User Manual
http://digital.ni.com/manuals.nsf/websearch/6E8329494F3955528625758300678D55
Joe Friedchicken
NI VirtualBench Application Software
Get with your fellow hardware users :: [ NI's VirtualBench User Group ]
Get with your fellow OS users :: [ NI's Linux User Group ] [ NI's OS X User Group ]
Get with your fellow developers :: [ NI's DAQmx Base User Group ] [ NI's DDK User Group ]
Senior Software Engineer :: Multifunction Instruments Applications Group
Software Engineer :: Measurements RLP Group (until Mar 2014)
Applications Engineer :: High Speed Product Group (until Sep 2008)

Documentation for register level programming of PCI-62XX cards

I'm looking for documentation for register level programming of PCI-62xx series cards. Does such a document exist?
Thanks

Scott,
At this time we do not have a comprehensive M Series RLP manual available. I was not aware of any plans to deliver this document last month, so you may have been given some incorrect information, in which case I apologize. Currently, we provide the register map along with several examples showing how to program the boards for different types of operations. If you have any specific questions, you can post them to this forum where our developers and other customers can help out. I hope this helps.
Jeremy

Register level programming for PCI 6733

The information provided online for RLP with PCI-6733 is very limited. Only the register map for PCI-6713 is provided @ http://www.ni.com/pdf/daq/us/release_ni67xx.pdf.
However, how the board maps its resources on the PCI bus is not clear. So could you please provide the following information
1. What the manual means by "Base Address" and "Window Address".
2. What is mapped by each of the boards BARs (Base Address Registers).
3. The difference of registers between PCI-6713 and PCI-6733.
If possible, could you please provide a detailed reference for this Analog Output board as for other boards, such as PCI-DIO-96.

Maybe you don't need the MITE manual after all. My documentation (from 2003) lists only the "DAQ-STC Technical Reference Manual - Part Number 340934B-01" and "PCI/PXI 671x/673x Register Map". I don't know where I got the information about the MITE -- one comment in my code suggests comedi.org, while another one mentions I started rewriting the code to get rid of the comedi stuff (so there must be information available from somewhere else, probably extracted from the DDK).
IIRC the MITE is only used once, for initialization.
I'm sorry I can't provice any code, but the driver I wrote is not openly available.
Warning: Some of the DAQ-STC information was wrong in the version I used, I had to use trial & error for some of the funtionality.
Check out:
http://digital.ni.com/manuals.nsf/websearch/E929838D7D0EE50986256728007FEADF?OpenDocument&node=132100_US
http://digital.ni.com/public.nsf/websearch/15f094f65a17e3af8625660d0018a20a?opendocument
Message Edited by Thorsten Jens on 08-22-2008 08:17 AM
Message Edited by Thorsten Jens on 08-22-2008 08:22 AM

Register Map Wizard

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