Restrict Important T- Codes

Hi,
I want to know, many users are having access to the important T-Codes : SU01, PFCG , etc.. which only authorization teams should have, but in earlier days roles was built like that, now if i make some role chagnes then it will mess up. Because many roles providing access to these T-codes.
So what iam asking could you tell me is there any other to restrict these particular transactions to some set of users? It should not reflect any impact on roles.
What is SHD0 transaction and what does it do ? Is there any way to fix this with the helpw of SHD0 transaction?

HI
To check for users assigned with a particular role, transaction SUIM is your answer. Here you can find a list of all the users who have been assigned a particular role.
Secondly, it is not possible to restrict users for executing any Tcodes without modifications in their assigned roles.What you can possibly do is copy roles, make modifications and assign these new roles with restricted access to the users.
Lastly, the transaction SHD0, is the SAP Transaction Code for Transaction and Screen Variants
Program/Report used to generate this transaction is SAPMSHD0.
I hope this helps you
Regards
Chen

Similar Messages

Restrict a t.code VK11 using Site as authorization object

Hi all,
We want to restrict VK11 t.code using Site as one of the authorizations. By default it has only Sales Org, Distr channel and division. I've added one more field for "Site" manually.
We have defined specific values for Site in authorization objects. Still system does not restrict VK11 executed by user as per site. It works with Sales org/Distr ch/Division. But it does not restrict Site-wise for that role.
Please help.
Regards,
Ankush

> I've never got past 'play dead' with such objects
Yip, I know that feeling. It is like when you leave home for a long trip having packed everything you need, but you still have the feeling that you have forgotten something important behind and will kick yourself when you need it.
> Can you please provide step by step instructions for that?
There is no step-by-step procedure nor medication to take for it. You just have to wait for it to dawn on you...
Enjoy the weekend and happy coding authority-checks,
Julius
ps: I heard that this feeling is also caused by the rising popularity of ABAP OO programming techniques, where the checks are often natively imbedded.

JAEHYLEE (R11i AP) Payables Open Interface Import REJECT CODE:NO TERMS

Purpose
Payables Open Interface Import REJECT CODE:NO TERMS
Symptoms
'EDI' Source로 invoice를 import할때 Payables Open Interface Import program 이 error로 종료된다
정상적인 에러 No Terms로 출력이 되나 , 데이타 상에는 아무 이상이 없으며
debug log file 의 reject code는 NO TERMS INFO라고 출력된다
REJECT CODE:NO TERMS INFO
CauseThe import program in procedure v_check_invalid_terms does not have exception handling. So, when ever it has exceptions like no_data_found or too_many_rows control was returning to the final exception block and the procedure was returning false to the calling procedure. Hence the error instead of Reject reason.
Bug 4704918 - APXIIMPT DOESN'T REJECT INVOICES WITH INCONSISTENT TERMS.
Solution
AP.N이상에서 patch 4755024를 적용
Please apply Patch 4755024 - 1OFF:4704918:AP.N:FP.G:11.5.10:APXIIMPT DOESN'T REJECT INVOICES
Reference
Note 359089.1

Have you customized/setup the Project Accounting Workflow builder. You need to do some setup for this workflow builder so that the project accounts can be derived properly.

What are the importent transaction codes in edi

what are the importent transaction codes in edi

hi,
=>sale - ALE Customizing
=>bale - Distribution Administration (ALE)
=>wedi - IDOC Type and EDI Basis
=>shdb - BDC (Transaction Recorder)
=>lsmw - LSMW
=>bapi - BAPI
=>spau - Display Modified DE Objects
=>spdd - Display Modified DDIC Objects
=>sara - central idoc archiving
=>stms - Transport Management System
=>wedi - IDOC Type and EDI Basis (IDOC Configuration)
=>bd21 - Analyze change pointers - create IDOC from change pointer
=>bd10 - Send Material Master
=>bd12 - Send Customer Master
=>bd14 - Send Vendor Master
=>bd50 - Activate Change Pointer for Message Type
=>bd55 - Conversion rule user exit (Link conversion rule user exit to the different system \ partner combinations)
=>bd54 - Maintain Logical Systems
=>bd71 - Distribute Customer Model
=>bd87 - Process Inbound IDOCs
=>bd88 - Process Outbound IDOCs
=>bdm2 - Cross-system IDOC Reporting
=>bdm7 - ALE Audit - statistical analyses
=>bdm8 - ALE Audit - sending confirmations
=>bd61 - Activate Change Pointer generally
=>bmv0 - Direct Input Data Transfer Administration
=>rz04 - Operation Mode
=>rz12 - RFC Server Group Maintenance
=>sar3 - Archiving object customizing
=>s001 - SAPoffice Inbox
=>s010 - Standards Texts (SAP Script)
=>se01 - Transport Organizer (Extended View - Performing and managing the transport of development object across different systems)
=>se09 - Transport (Workbench) Organizer (Controlling and keeping track of Development work and Development Objects)
=>se78 - Administration of Form Graphics (Import Graphics into SAP System)
=>se84 - ABAP Repository Information (search for SAP objects)
=>su01 - User Maintenance (Security)
=>su02 - Maintain Authorization Profiles
=>su03 - Maintain Authorizations
=>sm36 - Background Job Scheduling
=>sm37 - Background Job Monitoring (display batch jobs)
=>sm31 - Table Maintenance
=>sm30 - Calling View Maintenance
=>sm35 - Batch Input Monitoring (Error Logs)
=>sm50 - Process Overview
=>sm58 - Transactional RFC Monitoring
=>sm59 - Maintain RFC Destinations (Define RFC Configuration)
=>snro - Number Range Objects (for IDOCs)
=>we02 - Display IDOC
=>we05 - IDOC lists
=>we07 - IDOC statistics
=>we12 - Inbound processing of outbound file - convert outbound to inbound file
=>we14 - Process (dispatch) IDOCs through Port - RSEOUT00
=>we15 - Outbound IDOC from NAST - message control
=>we16 - Inbound File
=>we18 - Generate status file
=>we19 - Test tool
=>we20 - Add new Message Type to Partner Profile
=>we21 - Maintain Port Definition
=>we30 - IDOC Type development
=>we31 - IDOC Segment development
=>we41 - Process Code Outbound
=>we42 - Process Code Inbound
=>we46 - IDoc Administration
=>we47 - Status Code Maintenance
=>we57 - Assign function module to logical message and IDoc type
=>we63 - IDOC Type for Parser Output
=>we82 - Assign IDOC to Message Type
=>we60 - IDOC Documentation - IDOC Types
=>we61 - IDOC Documentation - IDOC Record Types
=>we81 - Create new IDOC Message Types
=>we82 - Assign IDOC to Message Type
=>pa20 - Display HR Master Data
=>pa30 - Maintain HR Master Data
=>bd59 - Create and assign Filter Object Type for Message Type
=>bd64 - Maintenance of ALE or any other Distribution Model
Hope this helps, Do reward.

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

FV11 Restriction at Co.Code level?

Dear MM experts,
I have checked up entire forum for the above subject matter.
Kindly let us know whether FV11 T-code is restricted at Co.code leve.
We have two company codes and userwise we would like to restrict while updating FV11 condition " JMIQ" .
FYI, updating FV11 for key combination " Plant/Vendor/Material"
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Kindly help
Thanx in advance.
Srihari

Hi,
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While maintening the condition records for the condition you can seperate the the condition values by co.code.
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How to restrict the t code BBPMAININT with DISPLAY Mode in SRM?

Hi experts,
I want to restrict the T code BBPMAININT : Maintain Business Partner with DISPLAY mode in SRM system?
Action Taken:1. I have restricted with "03 Activity" of all check and maintainauthorization objects for this tocde .
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Here are list of auth object I have restricted:
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Siva,
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hi dear,
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J1IC194J          Create annual return under section 194 J (Classic TDS)
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J1INUT Clear withholding tax on clearing accounts
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J1IS Process an excise invoice (outgoing) for other movements
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J2ID Archive tax deducted at source (TDS) documents
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J2IU Remit excise duty fortnightly
J2I9 Monthly CENVAT return
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Hai...
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Hi,
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