Review my ATM CLD practice paper?

Hey guys,
I have my CLD exam booked for early November and did a practice paper today. I was hoping somebody could take a look at my code and offer some constructive criticism?
It took the whole 4 hours and I would like to think it is a pass. I am worried there is not enough documentation.
What you think?
Lewis Gear CLD
Check out my LabVIEW UAV
Attachments:
ATM CLD Practise.zip ‏451 KB

Hey Lewis,
This looks good! There is a certification board this might get more traction on.
Some tips that helped me:
- Add a description and tip to all front panel objects (this was the first thing I did in my exam)
- Document everything - labels on all block diagrams, VI description for all VIs (including the main VI)
- Don't use non-default type-defined cluster constants (use default combined with Bundle By Name) - you will drop marks for this.
Overall this is a good effort. Get the documentation in, it's free marks
Come and say hello when you're sitting it!
Regards,
Peter D

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ATM CLD Practice Exam Example

Hello,
I am trying a somehow different architecture from what I am used to with the CLD ATM practice exam and I would appreciate any feedback. I am still hesitant about the "double queued message".
I'll appreciate your comments.
Regards.
Attachments:
ATM Simulator.zip ‏259 KB

Christian_M wrote:
I got the ATM in CLD Exam.
I think the code you posted is very good, but it is simply too much for CLD.
Don't try to create super-special-awesome architectures, instead use simple ones, e.g. I just used a statemachine which fullfills all the needs of the ATM. Keep in mind you only have four hours and with some exams you have lots of text to implement. More complex architectures are more difficulte do debug and there is not really time to debug.
So keep it simple!
Christian
Thank you Christian. Just yesterday I reworked this example using a simple state machine. Unlike with the architecture I posted here, with the simple state machine I had plenty of time to debug and test. So, you are probably right about keeping it simple. I guess I need to remember that the the CLD is a test and not a product to deliver to a client.

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Timing CLD practice exams

Hi,
I wanted to bring up this topic for those who are preparing for taking the CLD.
As you know there is a four hour limit for taking the exam. While preparing for the exam, using all the materials, webcast, and the certification discussion board, it is important ... , no critical, to clear your schedule and time yourself for a four hour exam. Twice.
Many developers get caught in the time crunch, both in their daily activities and in the test. Putting yourself in the position of having to face a hard deadline for completing the exam is a great wake up call. You don't want that call to be during the actual exam.
Timing your practice exams is a great way to experience the psychological pressures you will face during the four hours.
There is a wide spectrum of programmers that take the CLD, experienced pros, those who use it once or twice a week at work, advanced beginners, and all other experience levels. Preparing with a strict time limit gives all the broad spectrum of candidates the opportunity to see where their personal methods support or hinder the effort to complete in four hours.
In general, take no more than thirty minutes to read the specification, understand the specification, and plan your design.
Again, generally speaking, the last thirty minutes should not be used as a "last ditch" effort to start a new piece of functionality or race to a last minute addition. If a bug is introduced in this last half hour, the damage done to overall functionality could be much worse than the potential gain. One good use of the last thirty minutes is to continue testing integrated modules/SubVI's, to fix small discrepancies , to make one more verification that what you have already programmed is working correctly. One of my clients used to tell me "test, test, Test !"
Of course, it is impossible to give directions that will meet all individual methods. This is why taking a practice exam under strict time limits is a HUGE suggested best practice. You get to see first hand how your strategies and test taking methods fit the four hour time limit. You can plan and prepare your solution and methods, but until you time it firsthand, you are only measuring your knowledge of the methods. In most cases, nothing teaches faster than timing your sample exam and learning from your own mistakes.
If you are struggling with both implementation and timing, complete one practice exam without time, then take it again , timed, with just three and a half hours limit as you already know the specification.
One time saver is to document and label as you program. While you are in a section of code, document what that case, SubVI, or algorithm is doing. Right at the point of conception it is easy to jot down a one line description. Waiting until the end and then documenting all the work you have done is not as efficient as documenting "in the moment". You might be testing in the last thirty minutes and run out of time to document the complete application. Also, when you are working with already documented code, you are giving yourself a road map as you integrate modules or add functionality to the application. Try this while you are taking the practice exam.
I hope you find this advice helpful and something to think about, but more importantly I hope I have convinced you to take some practice exams with strict time limits. Although I have touched on a few topics, the focus here is to promote the timing your CLD practice exams in preparing for the CLD.
Mark Ramsdale
Project Manager and CLD
Customer Certification and Training at National Instruments

Jeff·Þ·Bohrer wrote:
RDarn the mobile interface.
Tim, I hear you. What do you consider to be a "normal project"?
PS My CLD-R is at 8:00am tomorrow.
"Normal" = project for actual work
Good luck starting in about 13 minutes!
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
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The Bare Metal provisioning best practices paper has been updated and is now available on OTN at the following location:
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Please review my CLD practice exam

Hi all,
I'm working my nerve up to take the CLD. If anyone has the time, I'd appreciate some advice on style, test rules, etc. based on my solution to the Traffic Light sample exam.
Seemed a lot easier than the car wash exam. Is this an older exam? How do the real tests compare to the practice exams? Any advice is much appreciated.
-Barrett
-Barrett
CLD
Attachments:
Stop Light Controller.zip ‏53 KB

blawson wrote: would a simple error dialog be all I'd need for error handling?
-Barrett
Message Edited by blawson on 11-16-2009 10:12 AM
Generally speaking, I think that the error dialog should suffice. I don't think I'm violating the NDA in saying this... (My sincere apologies to NI training & certification if I am - please delete my post if that's true) On exams I usually do something a bit more complex, but it's probably overkill. I usually run a separate loop in parallel and send my errors over there via a queue. That way errors don't hang up the application. Still, I use the stock error dialog (one of the two) in my error handler loop. I don't think I've ever lost points for that, to my recollection.
Also, regarding typedefs: To avoid orphaned enums that should be typedefs, I wrote something backwards on my forehead with a marker. (OK, not really.) "If it's a cluster or an enum, make it a typedef." Following this rule, I always start out with a typedef to begin with and thereby avoid the problem. My experience is that this almost always saves you trouble later on.
Free advice, for what it's worth.
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CLD Practice Review - Car Wash

Hey, so I've done all 4 available CLD Prep Exams. I was curious if I could get some feedback on the Car Wash. This, imo, was the easiest of them all and so I was wondering what kind of marks I would end up getting with the attached as the end result. Like, just how many "unnecessary bends" are present in my code? What does it need? The code is in 2011 SP1. Thank you.
Remember, code does exactly what you tell it.
Attachments:
Car Wash.zip ‏89 KB

Well while we wait for the thread to be moved here are some comments:
Your main has uninitialized shift registers for no reason. They should be initialized with constants.
All of your VIs are missing VI Icons
All of your VIs are missing VI Descriptions
Saved controls are also missing icon and description
Your front panel controls don't have tip strips, or descriptions
Wires are routed behind structures in a couple VIs
There are far too few comments. All cases in the state machine needs comments explaining what the state is for.
I also don't remember all the requirements so there is likly funcitonal things I don't remember. Like aren't controls supposed to be disabled when a car is going through the wash?
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Finished taking Sprinkler CLD Practice Exam

I am planning on taking my CLD this coming week, and just finished taking this practice exam. Since I studied the car wash and ATM solutions I decided to go for the Sprinkler practie exam. The "Sprinkler CLD.zip" file is the results of 4 dedicated hours of my Saturday.
I ran the VI analyzer on all VIs and CTLs and I'm not impressed with myself. Could somebody tell me how they think I would score?
I looked at the solution for the Sprinkler.vi and it's clear that my approach is nothing like the solution from NI. This could be a good or a very bad thing.
It appears quick comments could mean alot if the graders depend heavily on the VI Analyzer. It appears that I should have at least two comments in each VI, and not only have the documentation section filled in the VI but the same for controls.
It's clear that I missed some wires when I resized my case select boxes.
After finishing the exam and then looking back i see there is a possible lock out condition on initialization that would prevent the VI from reading the CSV file. I shouldn't have created a "READ CSV" State. If i would have placed the "READ CSV FILE" inside the "Power Up Configuration" state there would be no issues. I should have restarted labview in my last hour. If the VI starts up with the Water Pressure above 50% and No Rain then the CSV file is read and there is no problem. This would have been an obvious mistake had I restarted labview.
I realize that I missed some of the specifications. For example if it starts raining during a sequence it is suppose to restart the sequence, not pause it.
There are few comments in the code. I usually add many comments to my code, but this is my first time using a simple state engine.
At work I have a large infrastructure already in place complete with error handling and task management. I am also use to working on multiple monitors. During the test I only used one. Even if I didn’t pass this practice exam at least having a dry run outside my normal work condition was very good practice.
I spent time practicing earlier and can build the Timer.VI in about 8 minutes. A functional global timer seems to be a common theme in the practice exams.
Does anybody have any ideas or suggestions?
Do you think I would have passed the CLD exam with this test?
Comments?
Regards,
Attachments:
VI Analyzer Results.zip ‏4 KB
Sprinkler CLD.zip ‏377 KB

There are a lot of good things in your code, you are nearly there. I haven't run your code, so this is more style and documentation comments.
If I were you, I would concentrate on the following:
Wire Error through all your subVI's put your subvi code in an error/no error case structure. If you had done that, you didn't need the flat sequence structure in your code.
You haven't even wired error to the subvi's with error terminals, this will cost you points.
Label any constants on the block diagram.
Brief description of Algorithm on each VI block diagram.
You could have avoided using local variables, for example Run Selector as this control is available in the cluster. So just a unbundle by name would have given you the value of that control. If you do use them, then make sure you state why (for example efficiency etc.) in a block diagram comment.
Some subVis are missing VI documentation, this wont be taken lightly.
Using default value when unwired (for your while loop stop) is not recommended. This was specifically discussed during a CLD preparation class I attended not so long ago.
While icons are pretty, I wouldn't waste time trying to find glyphs for your subvi's just consistent text based icon scheme is perfectly acceptable. You can do this if you do have extra time, it wont fetch your extra points though.
LabVIEW 2012 has sub diagram labels, you can enable this by default in Tools>>Options, adding comments in each of the cases is recommended.
The main thing is time management and make sure you read other posts/blogs on CLD. I would also recommend quick drop, if you haven't started using this it may not be a good idea to do so now for your exam next week. But in general it is very useful and saves time.
Hope this helps.
Beginner? Try LabVIEW Basics
Sharing bits of code? Try Snippets or LAVA Code Capture Tool
Have you tried Quick Drop?, Visit QD Community.

ATM CLD Exam Solution: Feedback Welcome

Attached is my solution for the ATM Exam. It took about 6 hours to complete, but I think I could get it down to 4 (I took a significant detour).
I'd love to hear from fellow test takers or graders out there on the choice of architecture and readability.
Thanks,
Tom
Attachments:
CLD Sample Exam - ATM Machine - Tom.zip ‏295 KB

Here are a few more suggestions after reviewing your code.
Clean up your wires. There are unnecessary bends all over the place as well as wires that run back on themselves (Out of position property node).
Definitely get reid of all the property nodes. You really aren't using data flow with property nodes all over the place.
As mentioned earlier, everything including the subVIs eed to be documented.
Verify your functionality. This application doesn't meet the requirements. The out of position LED is not light properly for one. As mentioned your stop is not a graceful shutdown of the application.
Use a project for your application.
Consider placing your timing control in a subVI. You effectively have multiple copies of this functionality in your code.
Don't use the Wait VI for timing control.
As mentioned this really isn't a producer/consumer architecture. Take a look at the examples for how this normally looks.
All constants should be labeled.
Resize the front panel. Front panels should be size appropriately and shouldn't be a huge window with a few controls and indicators on it.
Resize the block diagram to fit on a single screen and avoid the need to scroll to see everything.
Make sure to align the controls and indicators are aligned on the front panel.
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My stoplight.vi for CLD practice exam

I am preparing for CLD and looking for comments on my implementation of the "stoplight" CLD example question. Any comment would be appreciated. Kudos will be distributed liberally.
The pdf for the example question is in this zip file:
ftp://ftp.ni.com/pub/devzone/epd/2419.zip
Attachments:
CLD_Traffic_Light.zip ‏42 KB
Sample CLD Exam - Traffic Light.pdf ‏350 KB

It looks like your code does everything that the clad exam wants. I see that you documented everything but the main vi. You might just want to explain what the purpose of the mian vi is. I think you code is simple and east to read. The state machine is simple and works good and everything seems to flow nicely. You document well what is going on in each loop.
I hope this was userful info.
Tim
Johnson Controls
Holland Michigan

CLD Practice exam

Could anyone offer up suggestions to better the code? I probably spent too much time getting it to work because when I stopped at four hours I realized I hadn't done half the commenting I wanted too.
Thanks in advance for any help or suggestions.
-Ian
Attachments:
CLD Exam - Car Wash.zip ‏97 KB

-Put a description of your top-level VI under VI Properties/Documentation. An over-all description of what the program does.
-Use wire labels where appropriate (such as your shift registers).
-I would use some sort of error handling and make sure all your property nodes are wired through with the error clusters. This will also help with flow control since most of your property nodes are not wired to anything.
-Mark is correct in using the Use Default if Unwired on the tunnels. Although this is programmatically correct, I avoid using this just for the sake of clarity on what the default value is. Wire a default constant to these. The reason you may get dinged is it's not self-documenting.
-Your shift registers are uninitialized in your main loop. Was this your intention?
-In SetAllIndicatorsOff.VI there is no need for the Array Size function. You can use auto-indexing on your For loop. Or you can input your cluster and cycle through your cluster elements inside the For loop which will eliminate the need for the cluster to array function.
-In StationStepper.VI, your inner case structure does nothing.
-In DefaultWash.VI, the operation does not seem to agree with the documentation. The High Pressure Wash is enabled regardless of which wash setting is selected.
-In NeedStationOne.VI, like the unwired default for tunnels, wire constants to the index array function. Necessary? No, but it's easier to see what the default settings are for the function, in this case 0 and 1; although your description of the VI mentions nothing about these selections (Under Body Wash and Bug Remover).
-In TimeElapsed.VI, position your controls and indicators on the FP in the order they appear on the connector pane. This makes it easier to follow with the context help. Unless you're opening this VI during run, you don't have to worry about the look and feel of the FP. You could make this VI simpler by using an FGV.
-Editne last thought, make sure you create a project from the start.
All together your programming style is clean and well documented. I would definetly concentrate more on getting the documentation down right than proper operation, and as Mark stated, check your spelling. It makes it harder to understand what your intentions are.
Reese, (former CLAD, future CLD)
Some people call me the Space Cowboy!
Some call me the gangster of love.
Some people call me MoReese!
...I'm right here baby, right here, right here, right here at home

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Hi Mark,
If you want i can take a look on it. We are using jdev 903/BIB903 accessing an AW created at Oracle OLAP 9205 with AWM. Faced a lot of problems to understand the metadata layer created to make Express work with RDBMS but system is up and running.
Please send it at [email protected] .
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CLD ATM Problem: How Did I Do?

Hello all,
I hope this is kosher to post. I've just finished my first CLD practice exam, the ATM problem. I've attached my solution. Cany any of you provide feedback as to how this would stack up on the actual CLD? Would it pass?
For one note, it uses a queued state machine (QSM) architecture. I became very comfortable with this at my previous job, but it's not one of the standard NI architectures, though it's very similar. It allows you to couple states and variant state data. Would something like this throw off the grader automatically?
My other concern is my use of local variables. Am I following standard practices?
All feedback welcome. Thanks!
Attachments:
ATM.zip ‏140 KB

LabVIEW being a data flow language should technically not need sequence structures. It is generally considered bad style using them as it is much better using error wires to sequence your code. In particular stacked sequence structures are frowned upon as they allow to pass data to subsequent states making it overall extremly hard to read and generally hard to maintain. And there have been calls in the past to remove them alltogether.
If you are using LabVIEW professionally maintainability is key. Consider a complex application that is badly written and that needs changing after you left the company. This will lead to a very disgruntled customer who might need to scrap the application completely and start from scratch ... don't come back to ask for a job reference in this case!
Abiding by the style guidelines and documenting properly means that another developer shouldn't take too long to understand what your thought process was and also minimises the risk of introducing notoriously difficult to track bugs like race conditions (e.g. use of local variables etc.). If you want to check how maintainable your code is you can easily check this with a small-to-mid sized application. Give it to one of your peers. Let them look through it for 20 min and then let THEM talk you through your code. If their face is blank you know you've got work to do.
I generally try my hardest to achieve in-software-synchronisation without the use of any sequence structures. E.g. through the use of queued states (if you have four operations that need to happen in succession you could use split these operations into four cases and simply enqueue all four states at once: sequentialisation successful).
As I said there is a use for (flat!!!) sequence structures. I occasionally use them in FPGA programming.
Edit: Considering that "only" 37.5% of the score come from functionality the CLD is an exam all about documentation and style. It proves that you can write your code well, and that if it is not working that someone else can pick it up and finish the job. That's different in the embedded developer exam for example ... there it is 50% functionality. Documentation and style only account 20% there (The remaining 30% are for architecture).

Sample CLD (Boiler Controller) Solution for Review

Hi,
I have solved the Boiler Control example, as part of my CLD practice.
Can you guys please review it?
I couldn't meet the timing deadline but I think I can do it with some practice.
Also please excuse the documentation part. I hav done almost nothing on that as of now.
I would like to see comments on architecture, functionality, code readability, etc.
Thanks in advance.
Moni
**If necessity is the mother of invention, I bet laziness is the father.**
Solved!
Go to Solution.
Attachments:
MySolution_BoilerControl.zip ‏111 KB

I'm studying for the CLD myself and haven't passed it, so take my comments with a grain of salt.
A few suggestions. They're all very minor.
1) For your next practice, take the last 10 minutes of the 4 hours and do documentation. Those are fast, easy points. It's even better if you document as you go - just type a quick description of what you're doing in each frame, and add documentation to your VI Properties (especially your main one).
2) This is very minor, but I noticed a lot of coercion dots. A Quick Drop and Ctrl+I will clear those out quickly.
3) I think you should hide your debug indicators for State Q. At least move them off to the side, away from the desired front panel.
4) Shift cluster should definitely be a typedef.
5) Is there a reason you used a "File Directory/Info" instead of a "Check if File Exists" function? This is more a curiosity question than anything; the way you coded is functional, but sort of indirect.
6) I'm not sure if the exact right values are writing for the log file, I see "6/27/2012::10:29 PM,Pilot Proved,29.59" as a line, and I would expect the Pilot value to be >30?
I think barring a slight lack of documentation, it looks great. It's very organized and it's clear in every state what you're doing.
I hope you pass! Good luck on your exam!
http://linkd.in/mikele

Review my ATM CLD practice paper?

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