RIO - Channel to channel skew

Question

This has been a difficult query to answer through my usual routes, so I'm hoping this finds a domain expert in the likes of Spex or similar.
I use a lot of R series and RIO devices for test and measurement systems. Mostly, the requirements for these are in the analogue domain, with relatively low speed requirements (10, 20 MHz) in the digital domain. My current favourite device is the sbRIO 9636, which is perfect for my sort of industrial processes - I can integrate it into a rackmount system without worrying about bulky cables, and usually it's able to do most of what I'm hoping it can.
I have a new process coming up which will require a greater channel count in order to accommodate analogue and digital DUTs. In addition, the digital clocked outputs it will have to measure will be more like 50 MHz max. Because I'd like to stick to the sbRIO if I can, my ideal solution would be similar to a 9626 with a 9693 with additional C-Series modules, but with access to additional DIO on the RMC. And yes, I'm aware of what that system will look like (without the need for a custom RMC ) I'm pretty sure that even at RMC digital inputs, I can probably get to 44 MHz (with no headroom for Nyquist, which isn't so much of a problem). I know RIO devices often quote 80 MHz as the input speed, but I'm also aware that most advice seems to suggest applications beyond 5 to 10 MHz carefully consider timing.
Previously, I discounted using a cRIO with 9403s for the high speed digital because of uncertainty over the channel-to-channel skew and propagation between the input pin and the FPGA. If I could be guaranteed a fixed latency between pin to FPGA with a finite but small skew, I would be comfortable with that, as I care most about missing edges and synchronisation between mutiple inputs from the same device. These days, especially with the newer Zynq chassis making them more attractive, it's worth revisiting...but still those questions remain about channel-to-channel skew.
For what it's worth, PCI/PCIe devices are out due to a compatibility issue with other hardware. USB devices are out due to a lack of robustness within my test environment (whether due to lack of strain relief on most USB connections or because Windows likes killing USB devices from time to time). I can't justify moving to FlexRIO due to cost either. With access to a variety of R series and RIO devices, I know I can benchmark some of this, but it'd be nice to hear from someone vaguely in the know.
So, after a long ramble, my questions:
1. What's the channel-to-channel skew like on board level IDC DIO for sbRIO devices (4x on 9626, 28 on 9636)?
2. What's the channel-to-channel skew like on C-Series modules through an RMC (e.g. a 9403 connected to a 9693)?
3. What's the channel-to-channel skew like on C-Series modules through a cRIO chassis (e.g. a 9403 through a 9068)?
4. Are there any other options I'm missing?
I'd be happy to explain more about my process requirements away from the fora, if helpful.

Answer 1

Whoops, had meant to use 9402 rather than 9403!
Propagation delay is usually the latency between input pin to FPGA. If this is constant, this isn't a particular problem for edge counting / quadrature decoding - I just know that when my FPGA registers inputs as being high on A and low on B, that was what they were some time ago. In the case of the 9402, the spec is 17 ns typical, 55 ns max (although I've also seen 50 ns somewhere). This might be an issue if you're trying to synchronise with some other process, such as a high speed analogue measurement, but if it's constant you can account for the phase introduced.
You should find, if you shove a 9402 or 9403 into a cRIO, that you can get in acquiring data at frequencies higher than 1/55n or 1/7u respectively - just that if you had an accurate way of measuring, you'd see level changes on those channels at some delay from the pin on the front of the module seeing a change.
What's more important for quadrature decoding is that the channel-to-channel skew for a device is short, typically of the order of nanoseconds. If you look at a typical line receiver, like the Texas Instruments SN65LBC175A or the Maxim MAX3095 etc, you'll notice their channel-to-channel and device-to-device skews are indicated. For an encoder measurement, this affects the maximum frequency you can count edges for. I know I can use one quad SN65LBC175A RS-485 receiver to receive four channels to within 1 ns of each other, and I can use a second and it will be within 2 ns of the other device. The propagation errors are an order of magnitude greater, but in the main this isn't an issue for most people trying to just count edges as per a counter application.
So...
- Propagation delays don't stop you sampling faster (I believe a 9402 can be driven to 80 MHz, as can a 9403)
- A constant propagation delay for a single device is acceptable, as I can usually adjust for the phase that this introduces if I really care about it
- Channel-to-channel skew is the main limiting factor for measurements of count edges...but this isn't routinely published data for C-series modules or RIO devices
If I could do everything straight into an RMC-mounted DIO or straight into the board level IO on an sbRIO, I'd probably be happy, but it would still be nice to know what the channel-to-channel skew is! As I've said, there's always the option of benchmarking any of the R-series/RIO combinations I own myself...but it would be nice to find the answer on a spec sheet somewhere.
I've opened a SR before and not really received much in the way of an answer, but short of spamming certain members of the FPGA team on the forum I don't know if it's answerable at all?