RSC Cards responding to SNMP?

I have several V880s with the RSC cards configured for remote access.
Recently, our security group contacted me and asked me to either turn
off SNMP or change the Public value. To which I responded "Huh?!
SNMP is not even running". (It's not)
Apparently, the IP address bound to the RSC card is responding to SNMP
requests. I checked all the variables with "rscadm show" and I dont
even SEE snmp anywhere, so I am at a loss.
Does anyone know:
a) Why the Sun RSC cards would respond to SNMP?
b) How I make them NOT respond to SNMP?

7 views and nobody has any idea?
:(

Similar Messages

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    Reset register: 40000000 ESRS
    RSC2 POST  -  Version 10-18-2000 0.7
    Dual Port Memory Test, PASSED.
    TTY External - Internal Loopback Test
    TTY External - Internal Loopback Test, PASSED.
    TTYC - Internal Loopback Test
    TTYC - Internal Loopback Test, PASSED.
    TTYD - Internal Loopback Test
    TTYD - Internal Loopback Test, PASSED.
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      Test for shorted address lines
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    Boot Sector FLASH CRC Test
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    RSC2 POST  -  Version 10-18-2000 0.7   Status = 00007fff
    Returned from Boot Monitor and Handshake
    Instruction CACHE Test
      DISABLE the I-CACHE
      ENABLE the I-CACHE
      Verify I-CACHE Performance Increase
    Instruction CACHE Test, PASSED.
    Memory Cells Test
      Counting UP:    Write data:  00000000
      Counting DOWN:  Read - Verify - Write data:  ffffffff
      Counting UP:    Read - Verify - Write data:  55aa33cc
      Counting DOWN:  Read - Verify - Write data:  aa33cc66
    Counting UP:    Read - Verify - Write data:  33cc6699
      Counting DOWN:  Read - Verify - Write data:  cc669955
      Counting UP:    Read - Verify - Write data:  669955aa
      Counting DOWN:  Read - Verify - Write data:  9955aa33
      Counting UP:    Read - Verify - Write data:  f0f0f0f0
    Memory Cells Test, PASSED.
    Data CACHE Test
      Verify D-CACHE Performance Increase
        D-CACHE Performance Increase I-CACHE Disabled
        D-CACHE Performance Increase I-CACHE Enabled
      Verify D-CACHE Memory
    Data CACHE Test, PASSED.
    Main Sectors FLASH CRC Test
    ERROR: RSC POST TEST
    H/W under test    = Flash Memory Data
        Test name     = FLASH CRC Test
        Subtest name  = Main Sector Flash Test
        Failure: CRC Error - ReFlash EPROM.
                 EPROM CRC: 98a2bebb  Calced CRC: 20e2c3d3
    END_ERROR
    Main Sectors FLASH CRC Test, FAILED.
    Load the RSC, then �Copying self to RAM...Done.
    Jumping to RAM.
    Waiting for boot protocol message...
    Did not get a boot protocol message.
    RSC <ESC> Menu
    f - Wait for flash download from host.
    C - Copy Boot Monitor from FLASHBOAT.
    j - Jump to main code (at 0x01010000).
    m - Run POST Menu.
        (Do not try this after a flash update of the boot monitor!)
    d - play DOOM
    s - Set clock speed
    e - Set external serial ports baud rate
    i - Set internal serial ports baud rate
    t - Toggle 'OK' flag
    R - Reset RSC
    b,h,w - Read byte/halfword/word
    B,H,W - Write byte/halfword/word
    r - Return to bootmon
    Your selection:
    SC <ESC> Menu
    f - Wait for flash download from host.
    C - Copy Boot Monitor from FLASHBOAT.
    j - Jump to main code (at 0x01010000).
    m - Run POST Menu.
        (Do not try this after a flash update of the boot monitor!)
    d - play DOOM
    s - Set clock speed
    e - Set external serial ports baud rate
    i - Set internal serial ports baud rate
    t - Toggle 'OK' flag
    R - Reset RSC
    b,h,w - Read byte/halfword/word
    B,H,W - Write byte/halfword/word
    r - Return to bootmon
    Your selection: f
    Copying self to RAM...Done.
    Jumping to RAM.
    Waiting for boot protocol message...
    Welcome to RSC bootmon v2.2.2
    Reset register: e8000000 EHRS ESRS LLRS CSRS
    RSC2 POST  -  Version 10-18-2000 0.7
    Dual Port Memory Test, PASSED.
    TTY External - Internal Loopback Test
    TTY External - Internal Loopback Test, PASSED.
    TTYC - Internal Loopback Test
    TTYC - Internal Loopback Test, PASSED.
    TTYD - Internal Loopback Test
    TTYD - Internal Loopback Test, PASSED.
    Memory Data Lines Test
    Memory Data Lines Test, PASSED.
    Memory Address Lines Test
      Slide address bits to test open address lines
      Test for shorted address lines
    Memory Address Lines Test, PASSED.
    Boot Sector FLASH CRC Test
    Boot Sector FLASH CRC Test, PASSED.
    Return to Boot Monitor for Handshake
    RSC2 POST  -  Version 10-18-2000 0.7   Status = 00007fff
    Returned from Boot Monitor and Handshake
    Instruction CACHE Test
      DISABLE the I-CACHE
      ENABLE the I-CACHE
      Verify I-CACHE Performance Increase
    Instruction CACHE Test, PASSED.
    Memory Cells Test
      Counting UP:    Write data:  00000000
      Counting DOWN:  Read - Verify - Write data:  ffffffff
      Counting UP:    Read - Verify - Write data:  55aa33cc
      Counting DOWN:  Read - Verify - Write data:  aa33cc66
      Counting UP:    Read - Verify - Write data:  33cc6699
      Counting DOWN:  Read - Verify - Write data:  cc669955
      Counting UP:    Read - Verify - Write data:  669955aa
      Counting DOWN:  Read - Verify - Write data:  9955aa33
      Counting UP:    Read - Verify - Write data:  f0f0f0f0
    Memory Cells Test, PASSED.
    Data CACHE Test
      Verify D-CACHE Performance Increase
        D-CACHE Performance Increase I-CACHE Disabled
        D-CACHE Performance Increase I-CACHE Enabled
      Verify D-CACHE Memory
    Data CACHE Test, PASSED.
    Main Sectors FLASH CRC Test
    ERROR: RSC POST TEST
    H/W under test    = Flash Memory Data
        Test name     = FLASH CRC Test
        Subtest name  = Main Sector Flash Test
        Failure: CRC Error - ReFlash EPROM.
                 EPROM CRC: 98a2bebb  Calced CRC: 20e2c3d3
    END_ERROR
    Main Sectors FLASH CRC Test, FAILED.
    Load the RSC, then �Copying self to RAM...Done.
    Jumping to RAM.
    Waiting for boot protocol message...
    Did not get a boot protocol message.
    RSC <ESC> Menu
    f - Wait for flash download from host.
    C - Copy Boot Monitor from FLASHBOAT.
    j - Jump to main code (at 0x01010000).
    m - Run POST Menu.
        (Do not try this after a flash update of the boot monitor!)
    d - play DOOM
    s - Set clock speed
    e - Set external serial ports baud rate
    i - Set internal serial ports baud rate
    t - Toggle 'OK' flag
    R - Reset RSC
    b,h,w - Read byte/halfword/word
    B,H,W - Write byte/halfword/word
    r - Return to bootmon
    Your selection: C
    Configure the jumper to read from FLASHBOAT, hit 'c' to continue Welcome to RSC bootmon v2.2.2
    Reset register: e8000000 EHRS ESRS LLRS CSRS
    RSC2 POST  -  Version 10-18-2000 0.7
    Dual Port Memory Test, PASSED.
    TTY External - Internal Loopback Test
    TTY External - Internal Loopback Test, PASSED.
    TTYC - Internal Loopback Test
    TTYC - Internal Loopback Test, PASSED.
    TTYD - Internal Loopback Test
    TTYD - Internal Loopback Test, PASSED.
    Memory Data Lines Test
    Memory Data Lines Test, PASSED.
    Memory Address Lines Test
      Slide address bits to test open address lines
      Test for shorted address lines
    Memory Address Lines Test, PASSED.
    Boot Sector FLASH CRC Test
    Boot Sector FLASH CRC Test, PASSED.
    Return to Boot Monitor for Handshake
    RSC2 POST  -  Version 10-18-2000 0.7   Status = 00007fff
    Returned from Boot Monitor and Handshake
    Instruction CACHE Test
      DISABLE the I-CACHE
      ENABLE the I-CACHE
      Verify I-CACHE Performance Increase
    Instruction CACHE Test, PASSED.
    Memory Cells Test
      Counting UP:    Write data:  00000000
      Counting DOWN:  Read - Verify - Write data:  ffffffff
      Counting UP:    Read - Verify - Write data:  55aa33cc
      Counting DOWN:  Read - Verify - Write data:  aa33cc66
      Counting UP:    Read - Verify - Write data:  33cc6699
      Counting DOWN:  Read - Verify - Write data:  cc669955
      Counting UP:    Read - Verify - Write data:  669955aa
      Counting DOWN:  Read - Verify - Write data:  9955aa33
      Counting UP:    Read - Verify - Write data:  f0f0f0f0
    Memory Cells Test, PASSED.
    Data CACHE Test
      Verify D-CACHE Performance Increase
        D-CACHE Performance Increase I-CACHE Disabled
        D-CACHE Performance Increase I-CACHE Enabled
      Verify D-CACHE Memory
    Data CACHE Test, PASSED.
    Main Sectors FLASH CRC Test
    ERROR: RSC POST TEST
    H/W under test    = Flash Memory Data
        Test name     = FLASH CRC Test
        Subtest name  = Main Sector Flash Test
        Failure: CRC Error - ReFlash EPROM.
                 EPROM CRC: 98a2bebb  Calced CRC: 20e2c3d3
    END_ERROR
    Main Sectors FLASH CRC Test, FAILED.
    Load the RSC, then �Copying self to RAM...Done.
    Jumping to RAM.
    Waiting for boot protocol message...
    Did not get a boot protocol message.
    RSC <ESC> Menu
    f - Wait for flash download from host.
    C - Copy Boot Monitor from FLASHBOAT.
    j - Jump to main code (at 0x01010000).
    m - Run POST Menu.
        (Do not try this after a flash update of the boot monitor!)
    d - play DOOM
    s - Set clock speed
    e - Set external serial ports baud rate
    i - Set internal serial ports baud rate
    t - Toggle 'OK' flag
    R - Reset RSC
    b,h,w - Read byte/halfword/word
    B,H,W - Write byte/halfword/word
    r - Return to bootmon
    Your selection: d
      OK.  You're DOOMED!
    RSC <ESC> Menu
    f - Wait for flash download from host.
    C - Copy Boot Monitor from FLASHBOAT.
    j - Jump to main code (at 0x01010000).
    m - Run POST Menu.
        (Do not try this after a flash update of the boot monitor!)
    d - play DOOM
    s - Set clock speed
    e - Set external serial ports baud rate
    i - Set internal serial ports baud rate
    t - Toggle 'OK' flag
    R - Reset RSC
    b,h,w - Read byte/halfword/word
    B,H,W - Write byte/halfword/word
    r - Return to bootmon
    Your selection: f
    Copying self to RAM...Done.
    Jumping to RAM.
    Waiting for boot protocol message...
    Welcome to RSC bootmon v2.2.2
    Reset register: e8000000 EHRS ESRS LLRS CSRS
    RSC2 POST  -  Version 10-18-2000 0.7
    Dual Port Memory Test, PASSED.
    TTY External - Internal Loopback Test
    TTY External - Internal Loopback Test, PASSED.
    TTYC - Internal Loopback Test
    TTYC - Internal Loopback Test, PASSED.
    TTYD - Internal Loopback Test
    TTYD - Internal Loopback Test, PASSED.
    Memory Data Lines Test
    Memory Data Lines Test, PASSED.
    Memory Address Lines Test
      Slide address bits to test open address lines
      Test for shorted address lines
    Memory Address Lines Test, PASSED.
    Boot Sector FLASH CRC Test
    Boot Sector FLASH CRC Test, PASSED.
    Return to Boot Monitor for Handshake
    RSC2 POST  -  Version 10-18-2000 0.7   Status = 00007fff
    Returned from Boot Monitor and Handshake
    Instruction CACHE Test
      DISABLE the I-CACHE
      ENABLE the I-CACHE
      Verify I-CACHE Performance Increase
    Instruction CACHE Test, PASSED.
    Memory Cells Test
      Counting UP:    Write data:  00000000
      Counting DOWN:  Read - Verify - Write data:  ffffffff
      Counting UP:    Read - Verify - Write data:  55aa33cc
      Counting DOWN:  Read - Verify - Write data:  aa33cc66
      Counting UP:    Read - Verify - Write data:  33cc6699
      Counting DOWN:  Read - Verify - Write data:  cc669955
      Counting UP:    Read - Verify - Write data:  669955aa
      Counting DOWN:  Read - Verify - Write data:  9955aa33
      Counting UP:    Read - Verify - Write data:  f0f0f0f0
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      Verify D-CACHE Performance Increase
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        D-CACHE Performance Increase I-CACHE Enabled
      Verify D-CACHE Memory
    Data CACHE Test, PASSED.
    Main Sectors FLASH CRC Test
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        Test name     = FLASH CRC Test
        Subtest name  = Main Sector Flash Test
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    Main Sectors FLASH CRC Test, FAILED.
    Load the RSC, then �Copying self to RAM...Done.
    Jumping to RAM.
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    C - Copy Boot Monitor from FLASHBOAT.
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    d - play DOOM
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    i - Set internal serial ports baud rate
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    TTYC - Internal Loopback Test
    TTYC - Internal Loopback Test, PASSED.
    TTYD - Internal Loopback Test
    TTYD - Internal Loopback Test, PASSED.
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    Memory Address Lines Test
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    Boot Sector FLASH CRC Test
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      ENABLE the I-CACHE
      Verify I-CACHE Performance Increase
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    Memory Cells Test
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      Counting DOWN:  Read - Verify - Write data:  ffffffff
      Counting UP:    Read - Verify - Write data:  55aa33cc
      Counting DOWN:  Read - Verify - Write data:  aa33cc66
      Counting UP:    Read - Verify - Write data:  33cc6699
      Counting DOWN:  Read - Verify - Write data:  cc669955
      Counting UP:    Read - Verify - Write data:  669955aa
      Counting DOWN:  Read - Verify - Write data:  9955aa33
      Counting UP:    Read - Verify - Write data:  f0f0f0f0
    Memory Cells Test, PASSED.
    Data CACHE Test
      Verify D-CACHE Performance Increase
        D-CACHE Performance Increase I-CACHE Disabled
        D-CACHE Performance Increase I-CACHE Enabled
      Verify D-CACHE Memory
    Data CACHE Test, PASSED.
    Main Sectors FLASH CRC Test
    ERROR: RSC POST TEST
    H/W under test    = Flash Memory Data
        Test name     = FLASH CRC Test
        Subtest name  = Main Sector Flash Test
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    Load the RSC, then �Copying self to RAM...Done.
    Jumping to RAM.
    Waiting for boot protocol message...[there is some interraction with the RSC, the menu was displayed and I have tried some functions.]
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    toostrow

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      Counting DOWN:  Read - Verify - Write data:  ffffffff
      Counting UP:    Read - Verify - Write data:  55aa33cc
      Counting DOWN:  Read - Verify - Write data:  aa33cc66
      Counting UP:    Read - Verify - Write data:  33cc6699
      Counting DOWN:  Read - Verify - Write data:  cc669955
      Counting UP:    Read - Verify - Write data:  669955aa
      Counting DOWN:  Read - Verify - Write data:  9955aa33
      Counting UP:    Read - Verify - Write data:  f0f0f0f0
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    Data CACHE Test
      Verify D-CACHE Performance Increase
        D-CACHE Performance Increase I-CACHE Disabled
        D-CACHE Performance Increase I-CACHE Enabled
      Verify D-CACHE Memory
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    ERROR: ALOM POST TEST
    H/W under test    = Flash Memory Data
        Test name     = FLASH CRC Test
        Subtest name  = Main Sector Flash Test
        Failure: CRC Error - ReFlash EPROM.
                 EPROM CRC: 00000000  Calced CRC: f6f497d5
    END_ERROR
    Main Sectors FLASH CRC Test, FAILED.
    Loading the r�Copying self to RAM...Done.
    Jumping to RAM.
    Waiting for boot protocol message...

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