RT FIFO Reference being "lost"

Hi,
I've got a create RTFIFO module and a RTWRITE module. The write is inside a timed loop (5ms time on a PXI-8196 controller). However, I'm having some trouble getting data out of my FIFO. In trying to solve the problem I noticed an issue with probes and trying to observe the "reference" to the FIFO thatis passed between the VIs.
If I put a probe on the RTFIFO reference before it is in the timed loop I see a zero value. Inside the loop a see a large value that makes sense if it is interpreted as a memory address but then going through a tunnel in a conditional inside the timed loop the reference becomes zero again.
This is troubling from my perspective because I don't understand how the RTFIFO write knows "where" to write data at this point.
I've attached a picture with probes in reasonable places that should help illustrate my convoluted description.
Attachments:
RTFIFOIssue.JPG ‏26 KB

Actually, you aren't seeing what you think you're seeing. Notice that the two probes showing the zeros are grayed-out. This means they haven't updated since they were created. The one on the left has no structure around it so I would guess that you created the probe after execution passed that point. The right-hand probe looks like its inside a case structure, but it also hasn't updated so the case its in apparently hasn't executed, or it was also created after the execution finished.
Mike...
Certified Professional Instructor
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wsterli wrote:
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"Cameron Purdy" <[email protected]> wrote in message
news:[email protected]...
One thing I would suggest is using WL's option to not replicate theentries
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>
Peace,
Cameron Purdy
Tangosol Inc.
Tangosol Coherence: Clustered Coherent Cache for J2EE
Information at http://www.tangosol.com/
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