SmartXplorer and Warning messages

Hi,
I need to generate a bit files using a design that uses almost allt he resources of the FPGA Spartan-6. To do so, I use SmartXplorer to get the better TimingScore possible for the Map and Place&Route.
However, I do not have a deterministic design, which means each time I make a new .bit (even if I do from the same design without changes) I can get a different design.
I need to write a test report and state the warning messages I get during the Xilinx Flow: synthesis, translation, map, place and Route, and Timings.
For Synthesis and Translation, I always get the same warnings.
But can I get the same warnings when using different runs from SmartXplorer?
Regards,

Thats strange. Ideally this should be deterministic. If we are chosing different options, then the results will vary.
Also, you can compare the checksum at each phase to find out more detailed information.
Compare the MAP summary information for differences.
The PAR placement pass checksum values (Xilinx Answer 15611) can be used to identify whether a particular placement pass generated the same results, and if not, determine where the two runs diverged.
http://www.xilinx.com/support/answers/23904.html
Hope this helps.
Regards
Sikta

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