Speed limit of Labview

Hello,
I would like to know until which treatment speed we can work with Labview. I work with a FPGA at 19200 Hz (T=50us), and I don't know if I can receive and read all the datas I send.
Thank you

Hi Ju!
Go through the attached presentation.
Hope so this will help you.
Kaustubh
VC (Pune)
INDIA
Jenilia D'souza
Attachments:
Advanced Application Timing with LabVIEW Real-Time1.zip ‏3000 KB

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My turn to ask a question. I read some- and everywhere the Athlon XP has a MHz limit of 2500. It seems to be so, but is it? I tried on my own to find an answer, and below is a result of that, but...
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Athlon XP and Sempron reached a speed limit
The main difference between the socket A processor nowadays seems to be in the architecture of the cache memories. The speed does not pass 2500 MHz. Why is that?
The first Athlons came in 1999. Their advantages compared to their competitor are/were the number of pipelines and calculation units:
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So what’s the problem? Speed it up!
Well, one bottleneck lies between the processor and the RAM memory, the Front Side Bus (FSB). The processor is much faster than the RAM and process data as they come by. To keep the processor busy mainly Intel invented a sort of pipeline, or ladder. The processor is working on every step.
Data is sent from hardware, like sound data or network data over the PCI-bus, graphics data over the AGP-bus, hard-disk data over the IDE (PCI-/SATA) bus, etc. The data comes in ones and zeroes in little packages, which make up complex instructions. For the processor to be able to efficiently perform the instructions they need to be sized down to simpler instructions, from CISC to RISC. (CISC codes is such a fundamental part of the PC history they must remain.) The sizing down is done in the very beginning of each pipeline. In later steps of the pipeline, the instructions are interpreted further and performed.
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So is this the simple basic calculation?
Athlon XP:s can do 2,5 instruction per clock-cycle in 10 steps per pipeline x the number of pipelines. The number of pipelines is limited by the number of instructions sent and their quality, 72 instructions at the same time. Can this be the reason for 2500 MHz limit?

Ok, reality check people...
Sharp, nice explanation, but you are wrong.
the x86 instruction set (including those nice MUL, ADD and other instructions) is a CISC instruction set.
The difference? A MUL takes 12 cycles, a DIV 40 or something...
RISC was a new computing architecture. Each instruction is simpler to allow higher execution frequency.
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- The second is that it ties down the unit. If you do a div in 40+ clocks, your integer unit is tied during this time.
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Pipelines are splitting the tasks in simpler tasks and executing each as independant as possible.
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This is the way intel followed. Prescott has a 25+ pipeline. The problem comes from branches. If you misspredict your branch, you have to flush the pipe.
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>
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Last edited by akurashy (2009-08-19 22:03:29)

invictus51: welcome to the boards, please read the Forum Etiquette, particularly around:
* don't necro-bump http://wiki.archlinux.org/index.php/For … Bumping.27
* ...and if you do feel compelled to, at least avoid power posting http://wiki.archlinux.org/index.php/For … mpty_Posts
Closing

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