[svn:osmf:] 14036: Tweaking sample to have the parallel element use a fixed size.

Revision: 14036
Revision: 14036
Author:   [email protected]
Date:     2010-02-08 06:31:10 -0800 (Mon, 08 Feb 2010)
Log Message:
Tweaking sample to have the parallel element use a fixed size.
Modified Paths:
    osmf/trunk/apps/samples/framework/LayoutSample/src/LayoutSample.as

Hi,
thank you for your fast reply. Please find attached my code where I marked the array creation with green circles and the control part with a red one. I removed all the other stuff and loops which are not relevant here (heart beat loop, value initialization, DMA fifo, etc). The sampling rate should be up to 50kS/s for capturing signals with a frequency of the range of 10 to 500Hz).
@ Spectre Dave:
I would like to do it in the FPGA because my host part (cRIO PPC) is already overloaded and I had a lot of problems to get it running and save the data to a file with the high sampling rate (50kS/s). I was thinking that simple array functions would be an easy thing for an FPGA. Or am I wrong??
Please let me know if you have any idea or if you need more information.
Thank you very much and best regards
Andreas
Attachments:
FPGAarrayProblem.png ‏189 KB

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