[Synth 8-3332] Sequential element (OUTMM_reg_P) is unused and will be removed from module

Actually i am getting this arning and post synthesis simulation does not match with behavioural simulation. I have read the other threads and tried options like keep_heirarchy ="true"  keep="true" changing simulation settings like 
flatten heirarchy - none , keep equivalent registers and resource sharing off . I also tried DONT_TOUCH it gave error saying the property does not exist for the type port and my port is OUTMM and from the error you can see that some flip flip regarding the OUTMM is getting optimized away.

Hi
Check below threads
http://forums.xilinx.com/t5/Synthesis/Synth-8-3332-Sequential-element-FSM-onehot-estado-reg-6-is/td-p/561308
http://forums.xilinx.com/t5/Synthesis/Vivado-2013-1-removing-quot-unused-quot-logic-need-to-understand/td-p/331557

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