Synthesis bug with SV packed multidimensional array slices

Question

I've been using SV packed multidimensional arrays to do things like representing a bus which is many bytes wide, e.g. a 128-bit bus can be declared like this:
logic [15:0] [7:0] myBus;
You should be able to write "myBus[15:8]" to get the upper 64 bits (8 bytes) of this 128-bit wide packed value. However, I've found that in some expressions this produces some very buggy behavior. I've reduced it to a simplified example, with comments to show what works and what doesn't.
`timescale 1ns / 1ps
module sv_array_select (
input logic sel,
input logic [3:0] [1:0] i,
output logic [3:0] outA,
output logic [3:0] outB,
output logic [3:0] outC
// Works; equivalent to assign outA = {i[1], i[0]};
assign outA = i[1:0];
// Works; equivalent to assign outB = {i[3], i[2]};
assign outB = i[3:2];
// FAILURE
// Synthesizes to equivalent of:
// assign outC[2:1] = sel ? i[2] : i[0];
// assign outC[3] = 1'bZ;
// assign outC[0] = 1'bZ;
assign outC = sel ? i[3:2] : i[1:0];
endmodule
 I get this result in Vivado 2015.2 and 2013.2, haven't tried other tool versions.

Answer 1

,
Yes, I can see that incorrect logic is getting generated by the tool.
I will file a CR on this issue and will let you know the CR number.
Thanks,
Anusheel
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