The core clock is slow or no core clock connected for this ILA or the ILA core may not meet timing.

Question

[Labtools 27-1395] Unable to arm ILA 'hw_ila_1'. The core clock is slow or no core clock connected for this ILA or the ILA core may not meet timing.
I have seen related forums but cant get any help. My timing is completely fine. I tried all JTAG frequencies from 1.5MHZ to `12 MHZ. My clk for ILA core runs at 100 MHZ.
If i remove one IP , then the ILA core works.  THE BD is attached. If i remove the right most IP(HLS_croppin) it works. I really cant understand. There is nothign worng with the timin in either case.

Answer 1

There are four possible reasons for this problem:
- The trigger condition is never met;
- The trigger clock (clock mapped to the ILA Core) is stopped;
- A known issue exists with the Storage Qualification feature;
- BUFG is not being used on JTAG CLK (for the ICON).
The trigger condition is never met
Check the message at the bottom of the ChipScope Analyzer window. If it is similar to "Waiting for trigger, Sample buffer has 0 samples(0%)," proceed as follows:
1. Go to "Trigger Setup" and "Trigger Immediate." If ChipScope Analyzer starts the acquisition and shows the samples (the waveform appears), your design is fine; the clock is running, but your trigger condition never occurs.
2. In the "Trigger Setup windows, ensure that you have set the condition correctly if you are sure that this event (the trigger condition) happens in your design.
The trigger clock is stopped
If the message at the bottom of the window is similar to "Waiting for Core to be armed, slow or stopped clock," the trigger condition is not the problem -- the ILA Core does not have a valid clock and is not able to start the acquisition. To fix this, ensure that you have mapped a valid clock (in ChipScope Inserter or ChipScope Generator). If you are not sure if the clock mapped to the ILA Core is running, try to connect your system clock instead (or a clock that you are sure is running).
BUFG is not used on ICON's JTAG clock
If the JTAG clock does not use a BUFG, the "Waiting for upload" message can appear.
In some instances, slowing down the cable speed might provide a suitable work-around.