Time loop clock

every time i sync my iPod touch the clock sets back to a random time and date. it's a pain!!! does any one know how to fix this?
my iPod touch has the january update and added features

Hello Ravens Fan
I have had an attempt (unsuccessfully) at your suggestion, but not much luck I'm afraid.
I'm kicking myself because I should know how to do this.
I have attached my attempt. Would you please take a look at it and see where I'm missing the next ingredient.
Kind regards
Ray
Attachments:
timed while loop.vi ‏8 KB

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  • Using NI-9411 in a timed loop clock less than 40Mhz...

    Hi,
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    So I had a derived clock of 38.75MHz but this time, before compiling, i have an error saying that theses inputs can't not work at with this time loop clock...
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    I know that a 9411 device can run in a SCTL at 40Mhz.
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    Can it be because I'm asking the same device to run 1 SCTL with DI0, DI1, DI2 at 40Mhz and 1 other SCTL with DI3 DI4 DI5 at a different loop rate.. (38.75MHz) ...
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  • Time loop 中的数组问题

    1. time loop 设定每100ms对采集卡的6个通道进行一次单点采样,如果要将每次采集到的数据存到通道对应的数组中,应该如何设计框图?
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    Hi.
    The only way to have a software-timed loop execute faster than 1kHz is to include code in it which will take precisely the time you need to execute, which is very very hard to determine. So, it seems like you would need LabVIEW RT to be able to use the 20MHz computer clock, or some extra hardware.
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    Attachments:
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  • Processing in Time Loop with microseconds.

    Hello,
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  • Time loop and events (again)

    Good morning,
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  • Need a dual time zone clock app that runs like a screensaver

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  • Time loop problem when add a parellel subvi in another time loop

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  • Time loop accuracy

    Hi,
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    Message Edited by Tobel on 01-17-2006 04:31 AM

  • What is the maximum number of the parallel blocks or maximum pair of shift register used in FPGA VI time loop with cRIO 9104?

      I am writing a FPGA VI with module cRIO 9104, I need to do a lot of parallel execution of inside a timed loop. In total, I have used 20 pairs of shift registers in the timed loop, which simply means there is 20 parallel exceution across ONE time loop. However, it tells me that there is an over-used of the FPGA resources in the compliation report. One is the Slices and the other is the number 4 of LUTS ( see the attached file), would the compile will be sucessful if I change it to ALL block diagrams cascaded in series without using any shift register accross the timed loop? And do you think that it is reaosnable to have 20 pairs of shift register arranged in parallel inside a timed loop.
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    Your compilation report has 2 useful numbers to help answer your question, I'll summarize:
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  • No 'time connected clock'

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    Power PC G4 emac combo 128MB Ram, iMac G5 1.8 GHz PowerPC G5 512MB Ram 10.4   Mac OS X (10.4)  

    Hi ali b,
    Unfortunately I had no luck with your suggestion re: deleting the file
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    Jane

  • Problema di drift usando una Time Loop

    Sto utilizzando un sistema con:
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    Hi
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    Bruno Costa
    Automation Engineer

  • Hi, I would like to ask about how to capture data from real time loop.

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    Typically you will have to use RT FIFO or Queue communication to avoid any impact to your time critical loop.
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    Christian

  • HT201250 Time Machine clock not rotating

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  • Timer on clock app dimmed

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  • While/time loop from pc clock

    Hi Guys
    I have some code that (currently) uses a while loop to periodically open a file and read from it (in its simplest form....and...the details are not germaine to this post)
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    Solved!
    Go to Solution.

    Hello Ravens Fan
    I have had an attempt (unsuccessfully) at your suggestion, but not much luck I'm afraid.
    I'm kicking myself because I should know how to do this.
    I have attached my attempt. Would you please take a look at it and see where I'm missing the next ingredient.
    Kind regards
    Ray
    Attachments:
    timed while loop.vi ‏8 KB

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