Timing Error by non diagram component

Hi All,
I am facing an issue while compiling my FPGA VI for rotational test durability of a shaft.
Error is given below
Compilation failed due to timing violations.
Click the Investigate Timing Violation button to display the Timing Violation Analysis window.
& when i opened timing violation analysis window it is given as attachment.
Now in this window show element & show path button are not active.
How can i know error is due to which block of my coding?
I am attching my coding also.
Kindly help?
Regards,
Vipin Ahuja
Attachments:
Error window.png ‏151 KB
rotationalfp10.vi ‏293 KB

hey thu^^,
I tried this with LabVIEW2013, FPGA module, NI5640R v1.7 drivers, and successfully compiled the example template. I'm attatching my screenshots. Please let me know if there is any difference between my experiment and yours.
Attachments:
XilinxOptions.png ‏15 KB
compilationSummary.png ‏23 KB
finalTiming.png ‏24 KB

Similar Messages

NI5640R FPGA non-diagram component compilation timing error

I've tried to rebuild the NI5640R example "ni5640R Template" without adding or changing anything.
Got timing error (see below), saying that requirement missed by 0.16ns, because of some non-diagram components: /sDac0Reset, /aDac0Reset_or00001, /aDac0Reset. Xilinx options were set to "use recommended settings".
I've tried this several times, always getting almost the same result. Another example: requirements missed by 0.40ns, because of /sDacSimultReset, /aDac0Reset_or00001, /aDac0Reset. This is still with recommended settings.
Then I tried to compile with design strategy "Timing Performance". 5 out of 6 times compilation failed with timing violation 0.30-0.50ns.
Then I tried to compile with design strategy "Balanced". This time it failed only 2 times out of 6 with timing violation 0.02-0.04ns.
I guess using the "Balanced" strategy works more or less, but maybe there is some better way to address this? I don't even need DAC in my project, so maybe there is a way to exclude it?
Solved!
Go to Solution.

hey thu^^,
I tried this with LabVIEW2013, FPGA module, NI5640R v1.7 drivers, and successfully compiled the example template. I'm attatching my screenshots. Please let me know if there is any difference between my experiment and yours.
Attachments:
XilinxOptions.png ‏15 KB
compilationSummary.png ‏23 KB
finalTiming.png ‏24 KB

Flex Diagramming Component Released

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yWorks has officially released a
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Hi ,
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" Run-time error '429':Active X component can not create an object ."

Hi,
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Now, coming to the point, when you are adding a member in the membersheet, you need to process the dimension. This requires the admin rights. So, please check the task profile of the user ID, with which you are trying from your system. This user ID should be the primary admin.
Hope this helps.
Additionally, can you please elaborate on the steps on what you followed for adding a member from the excel directly?

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