Translate C code into LabVIEW

Hi, I have a function in C/C++, and I am wondering how I can have it translated into LabVIEW.
Thanks,
Andrea

There are three ways to use the code in LV.
First create a DLL or .Net assembly and call it from LV.
Second use a Formula Node. You can enter your C code directly there.
Third rewrite the code in LV.
Which is approiate will depend on your Code.
Rewriting in LV will cost most work and you need to have a good experience in programming in C and LV.
Most language constructs of C are available in LV but not all, e. g. there is no while loop. The While loop in LV is a do { ...} while loop. It will execute at least once. For a while loop you must use a Case with a containing While loop. since your termination expression must be used twice create a subVI for it.
Another thing which will go not easy to handle is the switch statement. Basicly the Case structure is the same but you must take care of the following code in C:
case <value1>
case <value2>
break;
case <value3>
break;
You must handle this by additional nested Case structures.
Most runtime functins are available or can be build using two or more LV function, e. g. fprintf can be created by Format Into String followed by a File Write.
If your code contains functions pointer thats no problem. VI references are function pointers. Open VI Reference creates a function pointer and Call by Reference uses it.
Since you are mentioning C++ you may need to have a look to the object oriented programming in LV.
OK, I'm the last one, but Ihe written the most text and some hints.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

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Tutorial on integrating C/C++ code into LabVIEW (6.0 through 7.0)?

Where can I get a tutorial that will show me how to integrate C or C++ code into LabVIEW?

I would also check the Using External Code in LabVIEW manual, found here
Bilal Durrani
NI
Bilal Durrani
NI

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

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I need some insight on as to whether I can use all my HP-Basic code in labview or labwindows and how? Can I create dlls and call them into labview or use the code itselg in LabWindows?
Any information will be appreciated.

A very long time ago, there was a BASIC version of LabWindows. You could not convert a Rocky Mountain BASIC program directly, but it was a fairly simple fit. You could then translate that into C code automatically through LabWindows. That was one of its selling points; you didn't have to lose all of that old BASIC code. About 10 years ago, they decided to go with only a C version of LabWindows and renamed it LabWindows/CVI. This change was made because most people who were converting from BASIC to C already had and supporting two languages and a translator was very expensive (cost, memory, processing power, complexity, - expensive in every way).
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Hope that this helps,
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Bob Young - Test Engineer - Lapsed Certified LabVIEW Developer
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mailto:[email protected]

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Hello,
I wish to use the library functions written by Luminary engineers for their cortex-m3 controllers. If i wish to use these libraries written in C language in Labview, what i should do? There are large number of labraries are available in their websites. If any one has implemented these libraries in labview please write to me.
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Solved!
Go to Solution.

A bit off topic, and I believe it's been discussed int he Feedback board before.
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[email protected]
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Play_Movie_Current_Possition.vi ‏48 KB

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Play_Movie_Current_Position.vi ‏63 KB

Tips and best practices for translating C into LabVIEW? SERIOUS newbie...

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There's already a couple of good answers, but to add to #1:
You're clearly looking for a typical C-function. Any VI that doesn't require front panel opening (user interaction) can be such a function.
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Basically one function is one VI, although you might want to split it even further, dont create 3k*3k pixel diagrams.
Depending on the amount of calculations done in your If-Thens they might be sub vi's of their own.
/Y
LabVIEW 8.2 - 2014
"Only dead fish swim downstream" - "My life for Kudos!" - "Dumb people repeat old mistakes - smart ones create new ones."
G# - Free award winning reference based OOP for LV

Code to translate xml data into html using jaxp ?

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</body>
</html>
</xsl:template>
</xsl:stylesheet>

Must be something wrong with your XSL.
However apparently it was so urgent that you didn't have the time to look at what you posted. They just "fixed" the forum software and apparently it doesn't escape HTML that you type in any more. Or stuff that looks like HTML, either. So your post was unreadable.
If your deadline hasn't passed, try reposting that code surrounded by [pre] and [/pre].

I am trying to use generate code in signal express to import into labview.

I get this error when i try to generate code in signal express to export to labview . I have tries the error suggestions but I am still having problems. any help would be appreciated
The version of LabVIEW you are generating code into does not contain all the necessary SignalExpress support files. Make sure you launch the version of LabVIEW with SignalExpress support installed before generating code from SignalExpress. If you want to generate code into more than one version of LabVIEW, uninstall SignalExpress and all versions of LabVIEW except the earliest. Install SignalExpress, then install any other versions of LabVIEW. Copy the files from the vi.lib\express\SignalExpress directory of the earliest installed version of LabVIEW into the same sub-directory location of any other version of LabVIEW in which you want to include support for code generation.

Typically, this problem is repaired by following the directions on the error message. Since it was not, can you please give us more information so we can start determining the cause?
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Navigate to the drive you have LabVIEW installed on ( usually C: ) — C:
Change directory to the appropriate LabVIEW directory — cd "\Program Files\National Instruments\LabVIEW 8.2\vi.lib\express\SignalExpress". Change the LabVIEW version to the one you actually are using. Do a directory listing and redirect the output to a file — dir > filename.txt. You can use any full path for the filename.txt. If you specify a simple name, it will end up in the current directory.
Please post your project. Verify that you are using the version of LabVIEW you think you are by launching it before you start code generation.
Thanks for your patience.
Message Edited by DFGray on 08-28-2008 08:23 AM
Message Edited by DFGray on 08-28-2008 08:24 AM
This account is no longer active. Contact ShadesOfGray for current posts and information.

How to use matlab code in Labview without having MATLAB software. I tried to convert .m files into .dll files. But i could not do. Please help me out..

Please help me out...
Solved!
Go to Solution.

bombay wrote:
Yes. It can be done. But Math script can not evaluate all functions in .m files (There are some exceptions).
And those can perhaps easily be ported to LabVIEW/MathScript?
It is not sufficient to disregard running your Matlab code in LabVIEW based on a few exceptions without first thoroughly evaluating the impact they have.
If you want to stick with Matlab in your implementation, then there are other avenues than hypotethizing about the limited portability issues of using MathScript in your project?
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