Upgrade do Plano de Fotografia para o Plano Completo para Estudantes

Olá,
Gostaria de trocar o meu Plano de Fotografia pelo Plano Completo CC para Estudantes. Como faço, já que me associei ao Plano de fotografia há alguns poucos meses e o vencimento anual deste ainda está distante?
Obrigado,
Lucas

Upgrade single to all Cloud http://forums.adobe.com/thread/1235382 may help, but I do not know if this is for the education plans

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  • Creative MuVo TX FM Firmware Upgrade 1.18.02 - The End For Many Players - Par

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    >>Dear >>>>in my first mail I wrote already:>>>>After installing the recovery driver I run the >>firmware update again. It says that it found a >>device in recovery mode and more (pretty quick >>message) and after this it searches for this >>device - and does not find any device connected >>to an USB port.>>>> From this statement you can see that I installed the recovery drivers
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    >>>player from your computer. Press and hold the Play button while >>>connecting your player to your computer's USB port. Continue to hold >>the>>>Play button for about 0 seconds after connecting your player to your
    >>>computer. Release the Play button when the Find New Hardware dialog >box>>>>>>>appears on the computer screen. Did you encounter any issue?>>>5. Follow the instructions on the screen to install recovery drivers >>for>>>your player.>>>6. Double-click the firmware upgrade file and follow the instructions
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    >>>you further. Thank you. >>>>>>Best Regards>>>>>><name removed>>>>Technical Support>>>Creative Labs Asia>>>>>>To provide feedback on your "Creative Experience" please click on the
    >>>following link:>>>http://www.**bleep**.com/support/contact/welcome.asp?r=CLA&d=TS>>>>>>========== >>>DISCLAIMER >>>========== >>>This email and any attachments may contain private, confidential and >>>privileged materials for the sole use of Creative's intended recipient>>>>>and is not to be forwarded or copied to others. Any review, copying >or>>>>>>>distribution of this email or any attachments by others is strictly >>>prohibited. If you are not Creative's intended recipient, please >>inform>>>Creative immediately by responding to this email and thereafter >>>permanently delete the original and any copies of this email together
    >>>with any attachments. Thank you>>>>>>Original Message Follows:>>>------------------------>>>Thanks for your response. I am a bit confused since I answered many of>>>>>your questions in my last mail already. And I have been working with
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    >>>any case - you should warn the customers using this upgrade or take it>>>>>from your webpage. If you read my old mail - I tried the whole upgrade>>>>>on 2 different OS and 2 different Computers with your latest drivers.>>>>>>Best Regards,>>>>>>Peter>>>>>>>>>At 07:38 0.0.05 +000, you wrote:>>>>Dear xxxxxx>>>>>>>>Thank you for reaching us at Creative Technical Support; we >appreciate>>>>>>>>the opportunity to assist you.>>>>>>>>Based on the information you provided, may I know if are you using >the>>>>>>>>player on Windows XP>>>> or Windows 98? I would like to inform you that the player only >>support>>>>>>>>>>the below operating system:>>>>>>>>Microsoft? Windows? 98SE/2000/Me/XP>>>>>>>>You might like to consider the below factors when connecting your >>>player>>>>to the computer's USB port:>>>>>>>>. Make sure you have the latest drivers, especially USB, installed >>for>>>>your motherboard. If you're not sure, check with your motherboard >>>>manufacturer.>>>>>>>>2. Make sure your motherboard has USB v. ports, supplying at least
    >>>>500mA to the USB ports. If you're not sure, check with your >>motherboard>>>>>>>>>>manufacturer.>>>>>>>>3. Try unplugging all other USB devices from the system.>>>>>>>>4. If you're using a hub, try connecting the product directly to the
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    >>>>privileged materials for the sole use of Creative's intended >recipient>>>>>>>>and is not to be forwarded or copied to others. Any review, copying
    >>or>>>>>>>>>>distribution of this email or any attachments by others is strictly >>>>prohibited. If you are not Creative's intended recipient, please >>>inform>>>>Creative immediately by responding to this email and thereafter >>>>permanently delete the original and any copies of this email together>>>>>>with any attachments. Thank you>>>>>>>>Original Message Follows:>>>>------------------------>>>>=======================>>>>>>>>Subject: CLA (CTL) - Technical Support Request - (MuVo TX FM)>>>>Name: xxxxxx>>>>E-mail Address: [email][email protected]][email protected][/url]>>>>Country: Thailand>>>>Self Description: Advanced PC User>>>>------------------>>>>Support Inquiry: ID(3) My Creative hardware stopped functioning >>>>correctly >>>>Product: MuVo TX FM>>>>Serial Number: C6PF32477002804Z>>>>Date Of Purchase: /2/2005>>>>>>>>------------------>>>>Operating System: Windows XP>>>>Creative Model Number: MUVO TXFM 52 MB>>>>Computer Brand/Model: >>>>Processor/CPU: >>>>Memory: >>>>BIOS Type/Revision: >>>>System Board/Chipset: >>>>------------------>>>>>>>>Detailed Problem Description:>>>>I tried to update to the latest firmware >>>>MuVoTXFM_PCFW__8_02 since I stay in Thailand >>>>and need the Thai letters. I installed the >>>>recovery driver since the upgrade software >>>>required this and did exactly what is described. >>>>After installing the recovery driver I run the >>>>firmware update again. It says that it found a >>>>device in recovery mode and more (pretty quick >>>>message) and after this it searches for this >>>>device - and does not find any device connected >>>>to an USB port.>>>>>>>>I have tried this many times and even with the OS->>>>Win98. The upgrade software detects the device in >>>>recovery mode but after this nothing more >>>>happens - it does not find it on an USB-Port >>>>anymore. >>>>>>>>=======================
    Moderator note: Please remove the name of the advisor when posting up e-mails.
    Message Edited by Catherina-CL on 0-3-2005 2:4 PM

    This is part of the message since you cannot post such a long message in posting.
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    Here the Creative support story. The first mail is at the bottom. I had to make part and part 2 since you cannot post such a long message here.
    To: Creative Labs Asia Customer Support <[email][email protected]][email protected][/url]>Subject: Re: CLA (CTL) - Technical Support Request - (MuVo TX FM) (KMM7755874I6636L0KM)Dear,I know the solution long time already. I just wanted to test the support at Creative. The problem is real and forces owners of your players to buy a new one since their playes get useless after the upgrade. Not only that Creative puts a faulty upgrade on their homepage - their support is good for nothing. But this was a test of the Creative support. I hardly can believe that Creative is not in the position to solve a very simple problem caused by Creative - what has severe consequences for their customers. But this mail story confirms exactly this. So my advice to any customers - stay away from this company and their products - what is the final result of my test. If you want to know the solution for the problem please contact me again - I am glad to help such a poor company :-)))) For free? I am not so sure...since my player was not for free too...Best Regards,PeterPS: The product is still within the "police period" of my dealer. And I did not just buy the product. If you ever read what your system tells you (what I had to enter) - it was long time ago.
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    >distribution of this email or any attachments by others is strictly >prohibited. If you are not Creative's intended recipient, please inform>Creative immediately by responding to this email and thereafter >permanently delete the original and any copies of this email together >with any attachments. Thank you>>Original Message Follows:>------------------------>Dear ,>>I was talking about Win98SE. I guess there is are not many people using
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    Moderator note: Please remove the name of the advisor when posting up e-mails.
    Message Edited by Catherina-CL on 0-3-2005 2:43 PM

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    give me of good colors Pantone U in the screen.
    Then, I know in the printing that my color will be printed well, no
    worries but this display of screen is too bad it's a pity!
    It is not a progress but that is the way it is it is CC !
    Bye & thank's a lot for all
    Le 24/02/2015 16:19, Ton Frederiks a écrit :
    >
          Problème d'affichage des couleurs PANTONE solid Uncoated >
          Différence entre les versions CS et CC ?
    created by Ton Frederiks
    <https://forums.adobe.com/people/Ton+Frederiks> in /Illustrator/ -
    View the full discussion
    <https://forums.adobe.com/message/7225351#7225351>

  • PAR done but shows PAR Error on planahead 14.7

    hi,
    am getting PAR error while in log it shows PAR done!!!
    this happens only when i change the reset pin of my design from V5 to any other pin.
    my design consists of microblaze also.
    Thanks

    following is the logi file
    *** Running ngdbuild
    with args -intstyle ise -p xc6slx45fgg484-2 -dd _ngo -uc "top_module.ucf" -bm "top_module.bmm" "top_module.edf"
    Command Line:
    D:\InstalledSW\Xilinx147\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
    -intstyle ise -p xc6slx45fgg484-2 -dd _ngo -uc top_module.ucf -bm top_module.bmm
    top_module.edf
    Executing edif2ngd -quiet "top_module.edf" "_ngo\top_module.ngo"
    Release 14.7 - edif2ngd P.20131013 (nt64)
    Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
    Reading NGO file
    "D:/BEL_DRC/BEL_DRC/mohammad_ADC_july24/spartan6_adc2.runs/impl_1/_ngo/top_modul
    e.ngo" ...
    Gathering constraint information from source properties...
    Done.
    Annotating constraints to design from ucf file "top_module.ucf" ...
    Resolving constraint associations...
    Checking Constraint Associations...
    Done...
    Processing BMM file "top_module.bmm" ...
    Checking expanded design ...
    WARNING:NgdBuild:443 - SFF primitive
    'test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Perform
    ance.Decode_I/Using_FPGA.Gen_Bits[27].MEM_EX_Result_Inst' has unconnected
    output pin
    Partition Implementation Status
    No Partitions were found in this design.
    NGDBUILD Design Results Summary:
    Number of errors: 0
    Number of warnings: 1
    Writing NGD file "top_module.ngd" ...
    Total REAL time to NGDBUILD completion: 37 sec
    Total CPU time to NGDBUILD completion: 9 sec
    Writing NGDBUILD log file "top_module.bld"...
    NGDBUILD done.
    *** Running map
    with args -intstyle pa -w "top_module.ngd"
    Using target part "6slx45fgg484-2".
    Mapping design into LUTs...
    Running directed packing...
    Running delay-based LUT packing...
    Updating timing models...
    INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
    (.mrp).
    Running timing-driven placement...
    Total REAL time at the beginning of Placer: 17 secs
    Total CPU time at the beginning of Placer: 16 secs
    Phase 1.1 Initial Placement Analysis
    Phase 1.1 Initial Placement Analysis (Checksum:1f7146f2) REAL time: 19 secs
    Phase 2.7 Design Feasibility Check
    Phase 2.7 Design Feasibility Check (Checksum:1f7146f2) REAL time: 19 secs
    Phase 3.31 Local Placement Optimization
    Phase 3.31 Local Placement Optimization (Checksum:c84c17d2) REAL time: 19 secs
    Phase 4.2 Initial Placement for Architecture Specific Features
    Phase 4.2 Initial Placement for Architecture Specific Features
    (Checksum:fb9deab) REAL time: 38 secs
    Phase 5.36 Local Placement Optimization
    Phase 5.36 Local Placement Optimization (Checksum:fb9deab) REAL time: 38 secs
    Phase 6.30 Global Clock Region Assignment
    Phase 6.30 Global Clock Region Assignment (Checksum:fb9deab) REAL time: 38 secs
    Phase 7.3 Local Placement Optimization
    Phase 7.3 Local Placement Optimization (Checksum:fb9deab) REAL time: 39 secs
    Phase 8.5 Local Placement Optimization
    Phase 8.5 Local Placement Optimization (Checksum:fb9deab) REAL time: 39 secs
    Phase 9.8 Global Placement
    Phase 9.8 Global Placement (Checksum:fe784d) REAL time: 53 secs
    Phase 10.5 Local Placement Optimization
    Phase 10.5 Local Placement Optimization (Checksum:fe784d) REAL time: 53 secs
    Phase 11.18 Placement Optimization
    Phase 11.18 Placement Optimization (Checksum:bc17e6b8) REAL time: 1 mins 3 secs
    Phase 12.5 Local Placement Optimization
    Phase 12.5 Local Placement Optimization (Checksum:bc17e6b8) REAL time: 1 mins 4 secs
    Phase 13.34 Placement Validation
    Phase 13.34 Placement Validation (Checksum:ee3892b6) REAL time: 1 mins 4 secs
    Total REAL time to Placer completion: 1 mins 13 secs
    Total CPU time to Placer completion: 1 mins 9 secs
    Running post-placement packing...
    Writing output files...
    Design Summary:
    Number of errors: 0
    Number of warnings: 19
    Slice Logic Utilization:
    Number of Slice Registers: 2,768 out of 54,576 5%
    Number used as Flip Flops: 2,761
    Number used as Latches: 0
    Number used as Latch-thrus: 0
    Number used as AND/OR logics: 7
    Number of Slice LUTs: 2,495 out of 27,288 9%
    Number used as logic: 2,244 out of 27,288 8%
    Number using O6 output only: 1,810
    Number using O5 output only: 48
    Number using O5 and O6: 386
    Number used as ROM: 0
    Number used as Memory: 157 out of 6,408 2%
    Number used as Dual Port RAM: 64
    Number using O6 output only: 0
    Number using O5 output only: 0
    Number using O5 and O6: 64
    Number used as Single Port RAM: 0
    Number used as Shift Register: 93
    Number using O6 output only: 26
    Number using O5 output only: 1
    Number using O5 and O6: 66
    Number used exclusively as route-thrus: 94
    Number with same-slice register load: 90
    Number with same-slice carry load: 4
    Number with other load: 0
    Slice Logic Distribution:
    Number of occupied Slices: 1,309 out of 6,822 19%
    Number of MUXCYs used: 228 out of 13,644 1%
    Number of LUT Flip Flop pairs used: 3,563
    Number with an unused Flip Flop: 1,031 out of 3,563 28%
    Number with an unused LUT: 1,068 out of 3,563 29%
    Number of fully used LUT-FF pairs: 1,464 out of 3,563 41%
    Number of unique control sets: 256
    Number of slice register sites lost
    to control set restrictions: 1,096 out of 54,576 2%
    A LUT Flip Flop pair for this architecture represents one LUT paired with
    one Flip Flop within a slice. A control set is a unique combination of
    clock, reset, set, and enable signals for a registered element.
    The Slice Logic Distribution report is not meaningful if the design is
    over-mapped for a non-slice resource or if Placement fails.
    IO Utilization:
    Number of bonded IOBs: 4 out of 316 1%
    Number of LOCed IOBs: 4 out of 4 100%
    Specific Feature Utilization:
    Number of RAMB16BWERs: 32 out of 116 27%
    Number of RAMB8BWERs: 8 out of 232 3%
    Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
    Number used as BUFIO2s: 1
    Number used as BUFIO2_2CLKs: 0
    Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
    Number used as BUFIO2FBs: 1
    Number used as BUFIO2FB_2CLKs: 0
    Number of BUFG/BUFGMUXs: 14 out of 16 87%
    Number used as BUFGs: 14
    Number used as BUFGMUX: 0
    Number of DCM/DCM_CLKGENs: 5 out of 8 62%
    Number used as DCMs: 5
    Number used as DCM_CLKGENs: 0
    Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
    Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
    Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
    Number of BSCANs: 1 out of 4 25%
    Number of BUFHs: 0 out of 256 0%
    Number of BUFPLLs: 0 out of 8 0%
    Number of BUFPLL_MCBs: 0 out of 4 0%
    Number of DSP48A1s: 3 out of 58 5%
    Number of ICAPs: 0 out of 1 0%
    Number of MCBs: 0 out of 2 0%
    Number of PCILOGICSEs: 0 out of 2 0%
    Number of PLL_ADVs: 1 out of 4 25%
    Number of PMVs: 0 out of 1 0%
    Number of STARTUPs: 0 out of 1 0%
    Number of SUSPEND_SYNCs: 0 out of 1 0%
    Average Fanout of Non-Clock Nets: 3.63
    Peak Memory Usage: 536 MB
    Total REAL time to MAP completion: 1 mins 18 secs
    Total CPU time to MAP completion: 1 mins 14 secs
    Mapping completed.
    See MAP report file "top_module.mrp" for details.
    *** Running par
    with args -intstyle pa "top_module.ncd" -w "top_module_routed.ncd"
    Constraints file: top_module.pcf.
    Loading device for application Rf_Device from file '6slx45.nph' in environment
    D:\InstalledSW\Xilinx147\14.7\ISE_DS\ISE\.
    "top_module" is an NCD, version 3.2, device xc6slx45, package fgg484, speed -2
    Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
    Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
    Device speed data version: "PRODUCTION 1.23 2013-10-13".
    Device Utilization Summary:
    Slice Logic Utilization:
    Number of Slice Registers: 2,768 out of 54,576 5%
    Number used as Flip Flops: 2,761
    Number used as Latches: 0
    Number used as Latch-thrus: 0
    Number used as AND/OR logics: 7
    Number of Slice LUTs: 2,495 out of 27,288 9%
    Number used as logic: 2,244 out of 27,288 8%
    Number using O6 output only: 1,810
    Number using O5 output only: 48
    Number using O5 and O6: 386
    Number used as ROM: 0
    Number used as Memory: 157 out of 6,408 2%
    Number used as Dual Port RAM: 64
    Number using O6 output only: 0
    Number using O5 output only: 0
    Number using O5 and O6: 64
    Number used as Single Port RAM: 0
    Number used as Shift Register: 93
    Number using O6 output only: 26
    Number using O5 output only: 1
    Number using O5 and O6: 66
    Number used exclusively as route-thrus: 94
    Number with same-slice register load: 90
    Number with same-slice carry load: 4
    Number with other load: 0
    Slice Logic Distribution:
    Number of occupied Slices: 1,309 out of 6,822 19%
    Number of MUXCYs used: 228 out of 13,644 1%
    Number of LUT Flip Flop pairs used: 3,563
    Number with an unused Flip Flop: 1,031 out of 3,563 28%
    Number with an unused LUT: 1,068 out of 3,563 29%
    Number of fully used LUT-FF pairs: 1,464 out of 3,563 41%
    Number of slice register sites lost
    to control set restrictions: 0 out of 54,576 0%
    A LUT Flip Flop pair for this architecture represents one LUT paired with
    one Flip Flop within a slice. A control set is a unique combination of
    clock, reset, set, and enable signals for a registered element.
    The Slice Logic Distribution report is not meaningful if the design is
    over-mapped for a non-slice resource or if Placement fails.
    IO Utilization:
    Number of bonded IOBs: 4 out of 316 1%
    Number of LOCed IOBs: 4 out of 4 100%
    Specific Feature Utilization:
    Number of RAMB16BWERs: 32 out of 116 27%
    Number of RAMB8BWERs: 8 out of 232 3%
    Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
    Number used as BUFIO2s: 1
    Number used as BUFIO2_2CLKs: 0
    Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
    Number used as BUFIO2FBs: 1
    Number used as BUFIO2FB_2CLKs: 0
    Number of BUFG/BUFGMUXs: 14 out of 16 87%
    Number used as BUFGs: 14
    Number used as BUFGMUX: 0
    Number of DCM/DCM_CLKGENs: 5 out of 8 62%
    Number used as DCMs: 5
    Number used as DCM_CLKGENs: 0
    Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
    Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
    Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
    Number of BSCANs: 1 out of 4 25%
    Number of BUFHs: 0 out of 256 0%
    Number of BUFPLLs: 0 out of 8 0%
    Number of BUFPLL_MCBs: 0 out of 4 0%
    Number of DSP48A1s: 3 out of 58 5%
    Number of ICAPs: 0 out of 1 0%
    Number of MCBs: 0 out of 2 0%
    Number of PCILOGICSEs: 0 out of 2 0%
    Number of PLL_ADVs: 1 out of 4 25%
    Number of PMVs: 0 out of 1 0%
    Number of STARTUPs: 0 out of 1 0%
    Number of SUSPEND_SYNCs: 0 out of 1 0%
    Overall effort level (-ol): Standard
    Router effort level (-rl): High
    Starting initial Timing Analysis. REAL time: 8 secs
    Finished initial Timing Analysis. REAL time: 8 secs
    WARNING:Par:288 - The signal test_module_inst/mb_inst/dlmb_LMB_ABus[31] has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ra
    m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ra
    m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal test_module_inst/mb_inst/dlmb_LMB_ABus[30] has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ra
    m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ra
    m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ra
    m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ra
    m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    WARNING:Par:288 - The signal
    test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram
    32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
    Starting Router
    Phase 1 : 20567 unrouted; REAL time: 9 secs
    Phase 2 : 15210 unrouted; REAL time: 13 secs
    WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
    design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
    To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
    Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[0].clk_wizard_inst/dcm_sp_inst/CLKIN
    Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[2].clk_wizard_inst/dcm_sp_inst/CLKIN
    Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[3].clk_wizard_inst/dcm_sp_inst/CLKIN
    Phase 3 : 5729 unrouted; REAL time: 33 secs
    Phase 4 : 5729 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 35 secs
    Updating file: top_module_routed.ncd with current fully routed design.
    Phase 5 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
    Phase 6 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
    Phase 7 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
    Phase 8 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
    Phase 9 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
    Phase 10 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 50 secs
    Total REAL time to Router completion: 50 secs
    Total CPU time to Router completion: 50 secs
    Partition Implementation Status
    No Partitions were found in this design.
    Generating "PAR" statistics.
    Generating Clock Report
    +---------------------+--------------+------+------+------------+-------------+
    | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/mb_ | | | | | |
    | inst/clk_50_0000MHz | BUFGMUX_X2Y10| No | 960 | 0.064 | 1.774 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clk180 | | | | | |
    | _sig[0] | BUFGMUX_X2Y9| No | 28 | 0.057 | 1.766 |
    +---------------------+--------------+------+------+------------+-------------+
    | clk_rd_sig | BUFGMUX_X2Y4| No | 104 | 0.052 | 1.770 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clk180 | | | | | |
    | _sig[1] | BUFGMUX_X2Y11| No | 28 | 0.028 | 1.743 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clk180 | | | | | |
    | _sig[2] | BUFGMUX_X2Y1| No | 27 | 0.031 | 1.771 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clk180 | | | | | |
    | _sig[3] | BUFGMUX_X3Y8| No | 27 | 0.028 | 1.739 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/mb_ | | | | | |
    |inst/microblaze_0_md | | | | | |
    | m_bus_Dbg_Clk | BUFGMUX_X3Y13| No | 61 | 0.055 | 1.767 |
    +---------------------+--------------+------+------+------------+-------------+
    | clk_counter_sig | BUFGMUX_X2Y2| No | 2 | 0.002 | 1.738 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clkout | | | | | |
    | _wiz_sig[1] | BUFGMUX_X3Y5| No | 2 | 0.000 | 1.770 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clkout | | | | | |
    | _wiz_sig[0] | BUFGMUX_X3Y15| No | 7 | 0.045 | 1.767 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clkout | | | | | |
    | _wiz_sig[3] | BUFGMUX_X3Y16| No | 2 | 0.000 | 1.722 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clkout | | | | | |
    | _wiz_sig[2] | BUFGMUX_X2Y12| No | 2 | 0.000 | 1.766 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/adc | | | | | |
    |_wrapper_inst/clk270 | | | | | |
    | _sig[0] | BUFGMUX_X3Y14| No | 4 | 0.022 | 1.765 |
    +---------------------+--------------+------+------+------------+-------------+
    |test_module_inst/mb_ | | | | | |
    |inst/microblaze_0_md | | | | | |
    | m_bus_Dbg_Update | Local| | 20 | 4.177 | 6.233 |
    +---------------------+--------------+------+------+------------+-------------+
    * Net Skew is the difference between the minimum and maximum routing
    only delays for the net. Note this is different from Clock Skew which
    is reported in TRCE timing report. Clock Skew is the difference between
    the minimum and maximum path delays which includes logic delays.
    * The fanout is the number of component pins not the individual BEL loads,
    for example SLICE loads not FF loads.
    Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
    Number of Timing Constraints that were not applied: 1
    Asterisk (*) preceding a constraint indicates it was not met.
    This may be due to a setup or hold violation.
    Constraint | Check | Worst Case | Best Case | Timing | Timing
    | | Slack | Achievable | Errors | Score
    TS_test_module_inst_mb_inst_clock_generat | SETUP | 7.791ns| 12.209ns| 0| 0
    or_0_clock_generator_0_SIG_PLL0_CLKOUT0 | HOLD | 0.240ns| | 0| 0
    = PERIOD TIMEGRP "test_mod | | | | |
    ule_inst_mb_inst_clock_generator_0_clock_ | | | | |
    generator_0_SIG_PLL0_CLKOUT0" TS_ | | | | |
    sys_clk_pin HIGH 50% | | | | |
    TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
    pin" 50 MHz HIGH 50% | | | | |
    Derived Constraint Report
    Review Timing Report for more details on the following derived constraints.
    To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
    or "Run Timing Analysis" from Timing Analyzer (timingan).
    Derived Constraints for TS_sys_clk_pin
    +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
    | | Period | Actual Period | Timing Errors | Paths Analyzed |
    | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
    | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
    +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
    |TS_sys_clk_pin | 20.000ns| 5.000ns| 12.209ns| 0| 0| 0| 358509|
    | TS_test_module_inst_mb_inst_cl| 20.000ns| 12.209ns| N/A| 0| 0| 358509| 0|
    | ock_generator_0_clock_generato| | | | | | | |
    | r_0_SIG_PLL0_CLKOUT0 | | | | | | | |
    +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
    All constraints were met.
    Generating Pad Report.
    1 signals are not completely routed. See the top_module_routed.unroutes file for a list of all unrouted signals.
    WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not
    completely routed in this design. See the "top_module_routed.unroutes" file for a list of
    all unrouted signals. Check for other warnings in your PAR report that might
    indicate why these nets are unroutable. These nets can also be evaluated
    in FPGA Editor by selecting "Unrouted Nets" in the List Window.
    WARNING:Par:283 - There are 18 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
    Total REAL time to PAR completion: 53 secs
    Total CPU time to PAR completion: 52 secs
    Peak Memory Usage: 515 MB
    Placer: Placement generated during map.
    Routing: Completed - errors found.
    Timing: Completed - No errors found.
    Number of error messages: 0
    Number of warning messages: 23
    Number of info messages: 0
    Writing design to file top_module_routed.ncd
    PAR done!

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