User has over-constrained component

Hello,
        I'm getting an error like below for Ethernet
                Place:1318 - User has over-constrained component Soft_TEMAC/Soft_TEMAC/SOFT_SYS.I_TEMAC
                                     /GEN_GMII.I_GMII/gmii_interface/GEN_S6.GEN_IO.bufio_gmii_rx_clk. There are no placeable sites
                                     that satisfy the user constraints. Please review the user constraints on the driver component and the   
                                     load components of Soft_TEMAC/Soft_TEMAC/SOFT_SYS.I_TEMAC/GEN_GMII.I_GMII 
                                     /gmii_interface/GEN_S6. GEN_IO.bufio_gmii_rx_clk.
    I have gone through
        http://www.xilinx.com/support/answers/41988.html
  And have verified my all IOs are in the same bank
 Any one can please help
Thanks

Hello vijayak,
                     Thanks for the reply and sorry for the delay.
                     I went through the link and didn't come up with any idea which would help in solving my error.
                    The person there is just changing the ucf and assigning some different IOs which i can't do because for me they
are predefined. And has it is related to the clock i can think of routing the signals in same bank but that is also not possible because map process is not complete and .ncd file not generated.
                    I have a question like Even through all my signal are from the same bank and the IO driving the three Clock pins are on clock pins of FPGA they why the error comes up ??
Thanks

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