Using Timed Loops

I am trying to use a timed loop in my application. The only timing source available is the 1Khz clock on the CPU. I am using a PXI-8176 CPU in a PXI-1045 Chassis. I have found that the timed loop using the 1 kHz clock is not very accurate. When comparing the loop time versus a reference clock it lags by approximately 6 seconds in a 12 hour period.
Is there a way to use the 10 Mhz reference clock available on the PXI bus?
I have also tried using the counter on a PXI-6031E card but have not had much success.

I am trying to configure the timed loop to utilize the counter on a DAQ Card in lieu of the 1Khz clock on the CPU. I have included a vi demonstrating how I plan to implement this strategy.
I have also found that if a timed loop configured to process missed iterations is stopped and placed in an idle case, it will continue to count iterations based on its period and when made active again will process the missed iterations. Is this normal?
Attachments:
DAQmx Config for Timed Loop.vi ‏94 KB

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Crash when calling dlll built by LV using timed loop.

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Now the timed loop stops correctly everytime both in Labview environment and standalone exe. But when I call the dll version from C. The c program has no response after the program finishes.
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Unable to run Timed Loops

Bit of an odd one that had me scratching my head.
I have a development system consisting of a PC running a 7842R, acquiring analogue and digital data from the FPGA, loading it into a shared variable, and reading it out within a timed loop on the host as one parallel loop in a producer-consumer architecture.
All's well until one day last week when I noticed my host VI becoming unresponsive.
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A restart of the system, and rerunning the same VIs, and no problems since.
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3) Is there a way of recovering without a reboot? If it's a service crash, I'm hopeful.
The system will eventually form part of a production test environment, hence the query.
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FWIW, LV2012 SP1 32bit, Win7 64bit, Core2 Duo, 4GB RAM, tassels from the handlebars etc.
CLD

The timed loop is used to read all elements from a DMA FIFO and load them into a buffer FGV, which spits out packets of N samples long once they've assembled within the FGV. Ordinarily, I'd do this with a timed while loop and be perfectly happy to do so. However, the elements are actually an interleaved array, meaning that I have to demux them in the correct order that they were loaded.
I use timed loops for a number of reasons: on my current Windows host, I've found that using a while loop has caused me more problems with respect to disordered packets, and that at least with using multiple timed loops (two, at most), I can assign priority to the acquire loop. Finally, it's also a development platform, and will be deployed onto an sbRIO once the electronics integration is finished in a week or two!
W.r.t. system resources, there's very little else running on that system, but that doesn't normally stop Windows
I recognise it's not ideal to run a software timed loop under Windows, but when you cannot run a blank project with Optimizing timed loop rate.vi from the shipped examples with nothing else running, it makes me curious to know why!
CLD

DAQ and timed loop

Hi,
I have a question about DAQ and timed loop. I used timed loop while acquiring data. I need timed loop since I have tvo more loops in my application and ı need give some priority to them.
Data acquisition should have a high priority. But the example codes about DAQ always use wlile loop. Is this wrong to use timed loop in DAQ application, or there is a unexpected result about
this usage.

You could use timed loops in Data acquisition operations as well
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Suppose you have rate as 1000 samples /sec, in your DAQmx timing vi
In continuous acquisition, if you specify number of samples per channel as 500, instead of performing 2 iterations / sec to get your 1000 samples as your nor mal while loop would, your Timed loop will run for 1 sec and you will get an error that all samples could not be acquired

Write to XML File crashes when multiple Timed Loops present

Hello All,
It took me forever to track this bug down.
In this project we can edit operating parameters on the Host and send them down to an RT program in a cRIO-9025. The data is converted to XML and stored on the cRIO's disk.
Occasionally, the RT program would lock up and had to be rebooted.
It turns out that if you use Timed Loops , then a Write to XML File (or presumably any file write) will not return.
Attached is an example. This has 5 loops to make it crash faster, but it will eventually crash with only 2.
Paul J
Attachments:
XML Write test.vi ‏93 KB

Hello Chris,
I know that Write to XML File fails because I put in debug code in my actual program, a flat sequence which updated an indicator, and after the crash, the indicator had not updated.
Yes, I know that it replaces the file. It's a configuration file, not data gathering. This is just an example of the bug.
FYI,
I increased the period for the loop with the file save to 500msecs and it still crashed.
I then decreased it to 50 msecs, and replaced all of the other Timed loops with While loops and it does not crash, even though the file save takes much longer than 50 msecs, average ~150msecs.
I replaced the loop with the file save with a While loop while leaving the others as Timed loops and it does not crash.
So the bug is systemic and related to a file save in a Timed Loop when there are other Timed Loops.
I'm not looking for a solution, I'm only reporting a bug in Labview. The solution is not to use Timed Loops, especially, as you point out, when there is file saving. It cost me several days of dicking around to figure it out. Maybe someone can save some time if they find this.
Paul J

Sampling frequency in timed loop

Hi Guys. I used timed loop, is it my current sampling frequency from Figure 1 is 10kHz? if I want to change for example to 2.5kHz, should I just change 100 constant to 400?
Thank you.

mikeporter wrote:
Then, yes you are correct, but you have a problem in the form of those two express VIs. The way the code is written, the analog input and analog outptput tasks will be opened and closed with every iteration.
Sorry Mike, but that is wrong. We are dealing with a myRIO here, which behaves exactly the same as a cRIO. The IO is directly off of an FPGA. There is no task to open and close.
Though, I would question the actual sample rate. If the scan engine is being used, then the channels are actually sampled more like 100Hz. Please attach your entire project (put it into a zip file first) so we can get a little more insight to how things are set up.

Using timer/counter with PCI-6221/USB-6210 to control timed-loop VI

Dear all,
I need to ask about two devices and one of their functionalities, PCI-6221 and USB-6210. For our NI-based system, we need to control some timings in a Timed-Loop vi, for that currently we are using PCI-6221 and we give external TTL signal (at 1 kHz) to it,
recenntly we need to make some changes and for that we found USB 6210 DAQ to be more suitable, but we need to clear ourselves on some specific things.
Can the counter/timers functions available in the either PCI 6221 or USB 6210 can be used to control the Timed-loop VI by giving external clock or by using their own internal clock source?
Although we are using external clock with the PCI 6221 but we want to know about the usage of their internal clock, also are controlling timed-loop also possible for USB-6210
Also... What if we use the RTOS, are they still able to control the timed-loop VI without giving any 'EXTERNAL CLOCK' and using the internal clock sources of the DAQs
Waiting for reply,
Bests,
RaJaf
Solved!
Go to Solution.

Ben,
I having read previous email which I send earlier with general overview, we discussed in more detail within our team and I am giviing the specific answers.
Please check in RED the most recent answers. Blue are the questions/suggestions by your side.
1.    Using Internal hardware clock of PCI-6221 would enable us get rid of external clock, but how to divert the internal hardware clock to the current settings. Any idea (can you provide us with some reference manul for otherwise). I mean is there some flag-bit etc. or VI
2.       Is it also meant that with the installation of RTOS the timed-loop can directly get the timing source from the internal hardware clock PCI-6221? --- How???
3.       In order to make desktop to work as RT system, what is the hardware (motherboard, processor, etc..) requirement? What are the LabVIEW modules (specific name) that needed to be installed? Our platform is LabVIEW 8.6. (Currently we have windows-7 with i7 core processor)
What kind of application are you intending for this system? ---- high-speed laser scanning system.
Are you most concerned about accuracy, speed, or responsiveness? To control the laser mirror scanner to move at 1 kHz or 2 kHz speed. On the other hands, using PCI-5105 (128 MB memory) as a DAQ for real-time/on-the-fly data processing.
Bests,
RAJAF

Using NI-9411 in a timed loop clock less than 40Mhz...

Hi,
I'm using a cRIO for motion control. I have a counter that I modified a little bit (from the softmotion examples) and once compiled (unfortunately after 1 hour ...), I have an error saying that I couldn't acheive the desired timed loop clock of 40.4 MHz... the clock rate able to acheived was 40.16 MHz (really near)...
So I had a derived clock of 38.75MHz but this time, before compiling, i have an error saying that theses inputs can't not work at with this time loop clock...
The timed loop counter for this encoder only have to be more than 8000 Hz (1rev/s with 8000 pulses/revolution)
What can I do?
Thank,
Patrick

I know that a 9411 device can run in a SCTL at 40Mhz.
What I don't understand is that I can't run the loop below than 40Mhz.
I read in the FAQ that some device can not run above 40Mhz, but in my case, I want to run in slower....
Can it be because I'm asking the same device to run 1 SCTL with DI0, DI1, DI2 at 40Mhz and 1 other SCTL with DI3 DI4 DI5 at a different loop rate.. (38.75MHz) ...
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Patrick

Timed loop and CPU usage

Platform is WIN_XP Pro and machine is a P4 at 2.5Ghz with 512 Mb ram.
LV7.1 + PCI 6229
I am using 50ms Timed loop for running a state machine inside it
and also a whole lot of other things like reading / writing
DAQMx functions; file I/O functions and such. As the
project involves a main and sub-panlel set up local variables
could not be elimnated fully and there should be something like 150 of
them. But not all are accessed always - maybe about 15 of them at any
given time depending on the SM staus.
Problem :
Once started the "Finished late" indication is off and
the actual timing alternates between 49 to 52 ms. The CPU
usage is around 25%.
But as time goes by, the system gets unstable : After 15 minutes
or so, the Finished Late indication is always ON and the CPU usage is
gradually tending towards or exceeds 100%.
Obviously the machine control timing now gets affected and things slow
down badly. Closing the application ands restarting repeats the above
cycle.
I am at a loss to understand what is happening ? WIll
breaking down the single Timed Loop to multiple ones help ? WIll
that be an efficient way of parallel threading ?
I can post the code but its quite large and will do it as a last resort.
thanks
Raghunathan
Raghunathan
LV2012 to Automate Hydraulic Test rigs.

Hello,
It sounds like an interesting problem. It would be worth some experimentation to figure out what's going wrong - attempting to decouple major "pieces" of the code would be helpful. For example, you could try breaking your code into multiple loops if that makes sense in your architecture, but perhaps you could even eliminate all but one of the loops to begin with, and see if you can correlate the problem to the code in just one of your loops.
Another concern is that you mention using many local variables. Variable read operations cause new buffer allocations, so if you're passing arrays around that way, you could be hitting a problem of forcing your machine to perform many allocations and deallocations of memory. As arrays grow, this can be a bigger and bigger problem. You can use other techniques for passing data around your block diagram, such as dataflow if possible (just simple wires), or queues where dataflow can't dicatate program flow completely.
Hopefully looking into your code with the above considerations will lead you in the right direction. In your case, removing code so that you can identify which elements are causing the problem should help significantly.
Best Regards,
JLS
Best,
JLS
Sixclear

Questions about parallel and series sturcture in SCTL (single clock timed loop) in FPGA VI

I am using LV 8.2.
I have wriiten a FPGA VI, in this VI, there are 3 filters inside the SCTL (single clock timed loop) (I use the shift register to be the effect of unit delay). Would I save the resources of the FPGA used (such as slices and LUT) in the compliation report if I use 3 SCTL ( 1 SCTL contain 1 filter) and cascade them in series?
Thank you!

Sorry, I am afraid that you have misunderstood my meaning.
Here is the method you suggested before:
I mean I use the shift registers attached in the while loop, not in the SCTL. The number of shift registers used will not be decreased when we increase the number of SCTL in the second plate of the flat sequence structure. Totally , there are 6 pairs shift registers for 3 filters (1 filter needs 2 pairs). I mean I put the calculation parts, such as b0*x[n]+b1*x[n-1]+b2*x[n-2] inside the SCTL ( the operations of multiplication and add). Instead of putting 3 filters numeric operation part in one SCTL. will we reduce the resources used if we use 1 SCTL to do the operation parts of 1 filter? As the code inside each SCTL will be reduced.
Maybe you tell me if such approach will reduce the reosources used? Or there is no difference?
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LabVIEW RT, Timed loop, finished late, Call by reference

I have a timed loop triggered by the sample clock of a DAQ-Card. The sample Clock is 8 kHz and the loop will run with dt = 4. Normally the loop is running without finished late[i-1]. But from time to time it happens that the loop is running extremly longer which means instead of 0.5 millisec it needs 4 - 5 millisec. It seems this doesn't never occur while accessing DAQmx.
The application uses plugin technologies and some of the VIs in the timed loop are preloaded and called by Call by Reference.
Does those VIs inherit the priority, execution system and CPU of the timed loop?
The application is running on LV RT 2009 on a Dual core PXI-Controller. The timed loop is bound to CPU 1. There is no difference runinng the application from the development environment or as a startup application.
For the measuring test I modified the application in a way that I don't have:
disk access for storing the result file
TCP/IP communication
Controls on the front panel of the top level VI
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

To keep you informed:
I stripped the application and have left only the measurement storing module and the timed loop. The loop was using the microsecond timer running each 500 µsec. Additional all Non-Real-Time modules were loaded and only one module creates a XML string and sends it to the communication layer which will drop it because no TCP/IP port is open. The creation of the XML string is done each 300 ms.
In this case I don't have any finished late iterations
Next I added the DAQ Module. Now I get finished late again but with a lesser frequency as original.
I removed all unnesseccary tasks from the DAQ moulde leaving one task for a PXI-4204 for using as the clock source for the timed loop. No I get finished late seldom.
I removed the module which will send the XML string and I don't get finished late.
Next I was adding code to see memory allocation. I can when memory allocation is changing but it is not related to the finished late iterations.
Next time I have the chance to do more tests I will see which DAQ task triggers the finished late iterations. I have one AI task on a PXI-4204, 4 Counter tasks on a PXI-6602, 1 DI task on a PXI-6514, 1 DO task on a PXI-6514, 1 DI task on a PXI-6259, 1 DO task on a PXI-6259, 1 AO task on a PXI-6259 and 1 AO task on a PXI-6711.
The AI task on the PXI-4204 is running in Continous Sampling (Single Point HW Timed is not supported), all other tasks exept the DI and DO are Single Point HW Timed.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

Can I run a fast timed loop?

It appears that a timed loop cannot run faster than 100 hz. In other words, the "period" input for a timed loop cannot be less than 10. Is this true? I am using the Elapsed Time VI to measure time increments. The time increments output from this VI are at least 0.01 secs regardless of how fast I attempt to run the time loop. Perhaps the limitation lies in the Elapsed Time VI, not in the Timed Loop. Should I try a different approach to measuring the delta time between iterations of a time loop? TIA.
-jlivermore

Here's the simple way to measure loop timing:
Actually, what else is running in your loop (e.g. property nodes, DAQ, etc.)? Can you show us your code? What is your LabVIEW version?
Message Edited by altenbach on 09-29-2008 11:22 AM
LabVIEW Champion . Do more with less code and in less time .
Attachments:
MeasureLoopTiming.PNG ‏7 KB

Timed Loop in Producer/Consumer Loop

Hello!
I have a producer/consumer loop LabVIEW program setup to allow me to properly capture images that are quite large (8MP) at approximately 14 frames per second (FPS). The program works great when the consumer loop is a 'while loop' (records at 14fps no problem), but I wanted to make it into a timed loop, so that I may vary the FPS as required. An oddity arises when I do this. Anywhere below 12fps, the loop works fine and the data is recorded properly. However, when I bump it up to 13fps, the consumer calculated FPS goes haywire and starts jumping between ~9 and ~13fps (data processing gets bogged?). When I set the required FPS to 14, the loop executes at a steady 7FPS maximum. Is there something I can do to rectify this situation?
I have attached my .VI
Thanks in advance!
Solved!
Go to Solution.
Attachments:
ProcessSplitJPG-FPS.vi ‏100 KB

Palanski,
Are you using LabVIEW Real-Time? Timed loops in a windows OS don't really increase determinism more than a while loop with a wait until next multiple timer. Before you changed the producer consumer loop to include a while loop was the programming running correctly? You may also want to vuse the VI analyizer to see how long things are taking to run. I would leave the producer consumer loop in the traditional set up and change the FPS by controlling the wait timer, after benchmarking your code this should be done the same way as you have it for the timed loop
Sam S
Applications Engineer
National Instruments

Share cluster data between 2 timed loops

What is the best and safest way of sharing cluster data between 2 timed loops running. I could use locals, but that is risky, would shared variables work better? All I need to do is modify a couple of datatypes in a cluster that both threads use.
Thanks...

You could go the LVOOP route and create a singleton object. The object can be passed to parallel tasks an dsince it is singleton they will all share the same value. Ue of a DVR inside the object would allow you to have a single copy of the data. Your class would also give you the necessary accessors for reading/writing data.
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What is the best/most effective way to dynamically build a timed loop in LabView?

I am relatively new to labview (not to code in general) and am looking for the "LabVIEW" way to dynamically build a timed loop. This is what I am trying to accomplish:
I have several heaters controlled through labview using Labview's PID toolkit. This works great. I have no issues with DAQ in general. However, throughout an experiment, I want to change the set point of each heater. I could set this up fairly easily using either a timed loop or the wait vi if I knew exactly how many different set points there would be.
If possible, I would like to be able to read in a config file that includes the different times and set points for all heaters and dynamically create a loop that can handle this. I have tried using the Elapsed Time vi with an array of time targets; however that didn't seem to work.
Has anyone been able to do this? Does anyone know where I could learn about using LabView in this manner? All help is appreciated.

DHagan wrote:
I am relatively new to labview (not to code in general) and am looking for the "LabVIEW" way to dynamically build a timed loop. This is what I am trying to accomplish: I have several heaters controlled through labview using Labview's PID toolkit. This works great. I have no issues with DAQ in general. However, throughout an experiment, I want to change the set point of each heater. I could set this up fairly easily using either a timed loop or the wait vi if I knew exactly how many different set points there would be. If possible, I would like to be able to read in a config file that includes the different times and set points for all heaters and dynamically create a loop that can handle this. I have tried using the Elapsed Time vi with an array of time targets; however that didn't seem to work. Has anyone been able to do this? Does anyone know where I could learn about using LabView in this manner? All help is appreciated.
Write a tab-separated spreadsheet file makes it easy to use the write/read from spreadsheet files. Assuming you have a 2D-array of your times and set points it's just a question of setting up a for-loop going through the array row-by-row and extract the elements (expanded index array) to set your points and wait time.
/Y
LabVIEW 8.2 - 2014
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Using Timed Loops

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