VGA Controller Error upon Undock

Had to replace the hard drive on my X200. Everything reinstalled well. Downloaded all of the drivers on the Lenovo web site for this series. However when I try to undock the notebook, I receive an error stating the VGA Display Controller that is installed does not support Plug N Play devices and cannot be stopped. This disables the display on the notebook itself when I try to use it outside of the docking station. Is there a different driver I need to use besides the one on the support site?
Thanks!

Hi
I dont know which OS is preinstalled on your unit but please download the latest display driver and install it.
Toshiba download page is http://eu.computers.toshiba-europe.com/cgi-bin/ToshibaCSG/download_drivers_bios.jsp

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module counter( input wire clk,reset,
output wire hsync , vsync
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localparam HD = 800; // horizontal display area
localparam HF = 56; // front porch (right border)
localparam HB = 64; //right porch (left border)
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reg [9:0] h_count_reg ,h_count_next;
reg [9:0] v_count_reg , v_count_next;
reg v_sync_reg , h_sync_reg ;
wire v_sync_next , h_sync_next ;
wire h_end , v_end;
always @ ( posedge clk , posedge reset)
if (reset)
begin
v_count_reg <= 0;
h_count_reg <= 0 ;
v_sync_reg <= 'b0;
h_sync_reg <= 'b0;
end
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begin
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next ;
h_sync_reg <= h_sync_next ;
end
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assign v_end = (v_count_reg==(VD+VF+VB+VR-1)) ;
// below is the counter used to generate hsynch
always @(*)
if (clk) //50 Mhz pixel clock
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else
h_count_next = h_count_reg;
//counter used to generate vsynch
always @(*)
if(clk & h_count_reg == h_end)
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endmodule
The test bench is herewith attached:

Hi, this is my final code. Now signals hsync and vsync are throughout '1' but my output's red, green and blue are not displayed. Please help. I have attached the testbench too.
Code :
module vga_controller(input wire clk,reset,
output wire hsync,vsync,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
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reg v_sync_next , h_sync_next = 0 ;
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always @(posedge clk)
begin
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begin
h_count_next <= 0;
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end
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always @(posedge clk)
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h_sync_next <= 1;
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assign vsync = v_sync_next;
reg h_video_on,v_video_on;
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always @(posedge clk)
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coloroutput <= 0;
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begin
if(pixel_y<160)
coloroutput[7:5] <= 3'b111;
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coloroutput[4:2] <= 3'b111;
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