Virtex-5 power up sequence

Hi all,
I need to supply one bank with a VCCO of 2,5 V, and wonder whether it is safe to connect it to the same supply I use for the VCCAUX.
The datasheets and also AR # 34289 say, that 3-stated I/O is only guaranteed for the sequence int->aux->o, however I'm not sure if simultaneous ramp up does fulfill this requirement. AR # 34289 explicitly states for the Virtex-6 that simultaneous ramp-up is OK, but I could not find this information for the Virtex-5.
Any help is highly appreciated!
Stefan
 

Bill,
Re-reading through the whole thread, it is clear that in V5 we did not meet our goal of no glitch regardless of sequence.
If I recall, this was due to a design flaw in the level shifter circuitry.  It was the goal to keep all the level shifters in a benign state until DONE was asserted.
Thus, the sequence of being powered on and configured, to loss of Vccint, and restoration of Vccint is a violation of the power on sequence for V5.  That means that we do not know if it will glitch or not.
Sorry about the confusion.  As noted, the flaw was fixed in later technology nodes, but even then, there have been issues with power sequencing.  Safest is to follow both the suggested power on, and power off sequences in the data sheet.  Anything that will result in bad behavior (glitching), or be a reliability issue, is noted in the data sheet.
I agree that what you have done is the safest way to insure an output will not assert until DONE is asserted.
I would also be concerned that any outputs dring inputs will power ON the Vcco of the bank in question, so even if you remove Vcco, the bank may be powered from forward biased Vcco clamp diodes which are on every IO pin.
 

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