What DQS column locations & DQ master/slave settings do I pick in 10.1 EDK?

I am attempting to duplicate the FPGA synthesis flow using XST and ACE to boot Solaris on a Digilent board. I encounter some steps, warnings, and errors listed below that are not covered in the documentation I have. In following section 6.2 of the DV Guide,
after first running
rxil -device=XC5VLX110 sparc
I opened the ML505 project that I found in the Release 1.6 location at $DV_ROOT/design/sys/edk/system.xmp using XPS 10.1 (required to be 9.1i or later), which updated the project (I believe from EDK 9.2 in OpenSPARC 1.6) to the current release, including some manual updates required to be made because of incompatible cores as described in file Version_Changes.log:
The following files will be modified:
system.mhs
system.mss
The following changes will be made:
Core microblaze 7.00.b will be replaced by 7.10.a
Core plb_v46 1.00.a will be replaced by 1.02.a
Core mdm 1.00.a will be replaced by 1.00.b
Driver emaclite 1.11.a will be replaced by 1.12.a
The following changes need to be made manually by the user:
Core xps_ethernetlite 1.00.a needs to be replaced by 2.00.a
Core mpmc 3.00.b needs to be replaced by 4.00.a
Core clock_generator 1.00.a needs to be replaced by 2.00.a
In following the next step:
XPS 10.1 ³ Hardware ³ Generate Bitstream
I get warnings and errors in the XPS log file:
Check port drivers...
WARNING:MDT - PORT:IWAIT CONNECTOR:ilmb_LMB_Wait -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 196 - No driver found. Port will be driven to GND!
WARNING:MDT - PORT:DWAIT CONNECTOR:dlmb_LMB_Wait -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 232 - No driver found. Port will be driven to GND!
WARNING:MDT - PORT:bscan_tdo1 CONNECTOR:bscan_tdo1 -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_b\data\mdm_v2_1_0.mpd line 197 - No driver found. Port will be driven to GND!
WARNING:MDT - PORT:I_ADDRTAG CONNECTOR:ilmb_M_ADDRTAG -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 194 - floating connection!
WARNING:MDT - PORT:D_ADDRTAG CONNECTOR:dlmb_M_ADDRTAG -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 235 - floating connection!
WARNING:MDT - PORT:FSL0_S_CLK CONNECTOR:ccx2mb_0_to_microblaze_0_FSL_S_Clk -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 332 - floating connection!
WARNING:MDT - PORT:FSL0_M_CLK CONNECTOR:microblaze_0_to_ccx2mb_0_FSL_M_Clk -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\microblaze_v2_1_0.mpd line 337 - floating connection!
WARNING:MDT - PORT:bscan_tdi CONNECTOR:bscan_tdi -C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_b\data\mdm_v2_1_0.mpd line 190 - floating connection!
Constructing platform-level connectivity ...
ERROR:MDT - IPNAME:mpmc INSTANCE:DDR2_SDRAM PORT:MPMC_Clk0_DIV2 -
C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v4_00_a\data\mpmc_v2_1
_0.mpd line 2158 - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify
a connection in the MHS.
ERROR:MDT - IPNAME:mpmc INSTANCE:DDR2_SDRAM PARAMETER:C_MEM_DQS_IO_COL -
C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v4_00_a\data\mpmc_v2_1
_0.mpd line 197 - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify
a value in the MHS.
ERROR:MDT - IPNAME:mpmc INSTANCE:DDR2_SDRAM PARAMETER:C_MEM_DQ_IO_MS -
C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v4_00_a\data\mpmc_v2_1
_0.mpd line 198 - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify
a value in the MHS.
The sourceless connector error disappeared after I made the selections:
Xilinx Platform Studio > System Assembly View tab > Ports tab > DDR2_SDRAM > MPMC_Clk0_DIV2 > Make External
For the two remaining parameter errors I can choose:
Xilinx Platform Studio > System Assembly View tab > Configure IP...
Interface tab > Memory Interface Generator (MIG) Settings tab >
PDF Datasheet button leading to documentation of the parameters
and
C_MEM_DQS_IO_COL
C_MEM_DQ_IO_MS
For the ML505 board, what do I choose as a column location of left/center/right (00/01/10) for each of 8 DQS pins?
What do I choose as a value of master/slave (1/0) for each of 64 DQ pins?
A different top level block
rxil -device=XC5VLX110 iop_fpga
results in
XST ERROR : Could not open $DV_ROOT/design/sys/iop/iop_fpga/xst/iop_fpga.flist at $DV_ROOT/tools/perlmod/rxil,1.1 line 196.
Edited by: sparcMT1 on Dec 15, 2008 9:04 PM

Hi sparcMT1,
I'm not sure what the problem is. When we read in the 9.2 project into 10.1, it updated cores with very few problems.
One thing you can try is to do only the automatic updates. For example, even though XPS says that "these changes need to be made by the user", just leave the MPMC with version 3.0. I'm looking at one of our projects, and it seems that we did just that.
formalGuy

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Installing new internal HD-Master/Slave question

Hey gang. So you guys answered my original question of replacing the original hard drive in my G4 AGP Sawtooth. Thanks again! My next question concerns the whole Master/Slave aspect. The 2nd internal drive I put in several years ago is a Maxtor 120 or 160 gig. It was obviously a PATA drive but it's what's running OSX for me.
Does that mean it is the "master" drive? And when I install my new SATA PCI card will I want to run both drives off that? Probably so since it is the Serial kind but will I be able to connect the Maxtor 120gig PATA to the new PCI card? The new internal drive is a Seagate 500gig 7200.11 SATA. Should this be the "master" and then maybe slave the 120gig? I may be wayyy off on my terminology here but just wondering. The new PCI card is only 2-ports so I'm also assuming that I can only run 2 intern drives off of it. (oh, its a Sonnet Tempo 2-port Serial ATA PCI card)
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1. At the time of importing supplier catalog data into Master Repository through Import Manager, the Master Repository will be locked for Read Access through SRM-MDM Catalog Search UI???
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Hi Anshuk,
1. At the time of importing supplier catalog data into Master Repository through Import Manager, the Master Repository will be locked for Read Access through SRM-MDM Catalog Search UI???
Yes, at that time Master repo will locked and if you are using master slave scenario thencatalo 3.0 will log in slave repository.Basically MDM catalog 3.0 first find available slave then only move to master.
2. At the time of Master-Slave synchroniztion, which repository will be locked? Master or Slave or both? If both repositories are locked for searching, that means at that particular time, end users can't perform search
At this time slave that is under synchronization proces will locked not master.
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YES latest data in master only.High availability can achieved by what user set the synchronization frequency after each import or when.It is up to user only.
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What DQS column locations & DQ master/slave settings do I pick in 10.1 EDK?

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