What is the minimum pulse width output for PCI7831R?

I have a problem to generate the signal output by using PCI7831R.
I have used Labview FPGA program and PCI7831R with my experiment.
When I tried to output a signal which has a pulse width less than 2msec, Its pulth width becomes double or triple longer than I set.
    For example, if I set the pulse width 1msec, its output pulse width became 3msec...
                          But if I set the pulse width 2.5msec, its output pulse width is just 2.5msec.
Internal clock is 40MHz and theoretical rate is 53.5MHz. And the cycle time of main loop is less than 0.5msec.
(I believe those value are fine to generate the 1msec pulth width output.)
My questions are
-What is the minimum pulse width for PCI7831R?
-Do you have any idea to solve this problem?
I attached the picutre of my VI.
(because this picture is a little old, It has broken wires. But it is fine now.)
If conditions are all good, this VI will output the signal during "Injection Duration(micros)" micro-second.
Thanks,

I'm sorry I could figure out what was the problem.
And I also find the minimum output pulse width on the catalog (12.5nsec).
Thanks,
Kaoru

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