YN 622C pass-through TTL with 430 EX II?

Have Canon T5i, Canon 430 EX II flash.
I bought a set of Yongnuo YN622C radio TTL triggers, and they work great for OFF-camera TTL. I can set my 430EXII anywhere around a room and it shoots with perfect full TTL.
But when I have the YN622C on the Camera hotshoe, then put the 430EXII on top of that, right on the camera, the flash fires only as a manual flash.
The YN622C is supposed to have "pass through" ability - passing TTL settings through to the 430EXII mounted on top, but mine is not working. I want to have one TTL flash on top of the trigger, on the camera, for a fill flash, and then another flash on the remote trigger for an off-camera flash.
Has anyone else used these triggers with success? Do I just have a set of faulty triggers that should be returned? or is there some special trick that I'm missing to get TTL pass through?. It seems awfully strange that they work for OFF-camera TTL, but do not work when everything is mounted directly to the camera.

You should be able to have "pass through". It seemed to work Okay when I tried it.
I would suggest doing a Reset/Clear to default.
Here is a link to a very good resource for using the YN-622C. https://docs.google.com/file/d/0B77OmmGIg0gMVFpqNkpBYXBHajA/edit
Mike Sowsun
S110, SL1, 5D Mk III

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Dear experts,
I am currently working on a digital triangular shaping using the 7966R FPGA + 5734 AI. I am using LabView 2012 SP1.
Some days ago I have encountered a problem with my FIFOs that I have not been able to solve since. I'd be glad if somebody could point out a solution/ my error.
Short description:
I am writing U16 variables between ~32700-32800 to a U16 configured FIFO. The FIFO output does not coincide with the data I have been writing to the FIFO but is rather bit-shifted or something is added. This problem does not occure if I execute the VI on the dev. PC with simulated input.
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The Problem:
To reduce the amount of FIFOs needed I then decided to interleave the data and to use only 2 FIFOs instead of 4. You can see the code in the attachment. As you can see I have not really changed anything to the code structure in general.
The input to the FIFO is a U16. All FIFOs are configured to store U16 data.
The data that I am writing to the FIFO can be seen in channel 0 of the output attachment.
The output after passing through the two FIFOs can be seen in channel 2 of the same picture.
The output after passing through the first FIFO (times 2) can be seen in channel 3 of the picture.
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Bjorn
Attachments:
FPGA-code.png ‏61 KB
FPGA-output.png ‏45 KB

During the last couple of days I tried the following:
1. Running the FPGA code on the development PC with simulated I/O. The behavior was normal, i.e. like I've intended the code to perform.
2. I tested the code on the development PC with the square and sine wave generation VI as 'simulated' I/O. The code performed normal.
3. I replaced the FIFOs with queues and ran my logic on the dev. PC. The logic performed totally normal.
4. Right now the code is compiling with constants as inputs like you suggested...
I am currently trying to get LabView 2013 on the development machine. It seems like my last real hope is that the issue is a bug in the XILINX 13.4 compiler tools and that the 14.4 tools will just make it disappear...
Nevertheless I am still open for suggestions. Some additional info about my FIFOs of concerne:
Buffer 1 and 2:
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- Elements Requested: 1023
- Implementation: Block Memory
- Control Logic: Target Optimal
- Data Type: U16
- Arbitrate for Read: Never Arbitrate
- No. Elements Per Read: 1
- Arbitrate for Write: Never Arbitrate
- No. Elements Per Write: 1
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