Compatibility of Pattern I/O with a PXI-6533 card with real time application

Question

Hi,
I use a PXI-6533 card on a chassis with a PXI-8145 RT controller. I want to acquire 32 bits of data with this card at 1,25 kHz. These data are generated by an external FPGA card together with a clock signal. Referring to the 6533 documentation, a simple way to synchronize the acquisition is to use pattern I/O, entering the clock signal on the REQ pin. I tried the LabVIEW example Cont Pattern Input.vi. It seems to go well, but it does not work when I change this .vi priority to Time-critical or any higher priority than normal. Is there an incompatibility between this type of acquisition and real-time ?

Answer 1

Hi,
Sorry for this late answer, I effectively added a �wait until next ms function� in the time-critical loop and it seems to work. In fact, I don�t see exactly how, but it works with 1ms up to 50 ms.
Nevertheless, the next step is to add the content of this example in a more complex system with a communication loop to transfer the acquired data to the Host PC. I already have such an architecture, with a �time-critical priority� .VI to read the data at 1.25 kHz and a RTFIFO to transfer them to a second �normal priority� .VI loaded on the PXI, that ensures a TCP communication with the HOST PC. This architecture works correctly on another application with an internal clock, BUT doesn�t with this example, even with your solution.
In
fact, it seems to work when I put the two .VIs loaded on the PXI in �normal� priority, but with a tremendous jitter (the frequency varies from 1 to 2 kHz) and a scan backlog that gets full very fast. Then, the PXI crashes as soon as I change any priority.
You�ll find attached these three .VIs and I hope this could help to find a solution.
Cordially
PS: Since we started this thread, I�m in relation with NI Support France on that subject. Nevertheless, we haven�t found any solution yet and any new idea is welcome !
Attachments:
HOST_Comm.vi ‏532 KB
RT_Comm.vi ‏265 KB
TCLoop.vi ‏256 KB