Finite cheduling

Dear Seniors,
Please tell me how to configure finite scheduling becase i am giving demand in MD61 by Confiming the work center capacity and i run MRP. and i convert palnned order to production order for two days in advance, then i want system should schedule that order by considering pendeng order.
how it is possible
Faisal
Edited by: Muhamed Faisal on Nov 25, 2010 2:34 PM

1. In the wc ensure that the Finite scheduling tick is done in the capacity.
2. all the required capacity formula / values are all maintained.
3. Now when you run the MRP withe lead time scheduling then the planned order will be genreated.
4. After this you can use the CM21 graph plg table to do the scheduling.
since you are taling about the backorder , then you need to reschedule
ie) for examle
if you have a produciton order which was planned to completed by nov 24 but still in progress then you need to reschedule the same.. else it will not book the capacity ..
this also applies for any open order .
Kindly let me know your feedback
Reg
dsk
Edited by: DSk on Nov 25, 2010 3:13 PM

Similar Messages

Changing from continuous to finite sampling

Hi All,
I'm programming the 6602 with DAQmx 7.4 Ansi C API. This is pretty small issue, but since it might be a bug I thought I'd post it anyway. When I run a counter input task with implicit timing (say period or frequency measurement) in continuous sampling mode everything works fine - the task can be restarted after it has been stopped without any problems. The same goes for finite sampling mode. However, if I run the task in continuous mode, stop it, switch to finite mode and run it again, then it never seems to finish. More specifically, even after all the samples have been read, neither DAQmxIsTaskDone() nor DAQmxGetTaskComplete() indicates that the task is completed. Also, the done event callback function is not executed. Consequently, my thread for reading the data and saving it to file never completes even though all the data is read from the buffer. Anyone know what is going on here? As a workaround, maybe I could monitor the amount of data read from the buffer and stop the task explicitly once the requested number of samples have been collected, but I'd rather have it complete naturally......
Jeff

Hi Axiom-
I have been able to replicate the same behavior you're seeing using NI-DAQmx 7.5, the most recent released version. It seems that this may be an issue and I will file a corrective action request for the issue.
For the timebeing, your suggestion to monitor the number of samples read and programmatically stop the task seems like a solid workaround. Please post back if you have any additional questions.
Thanks for keeping us on our toes!
Tom W
National Instruments

Changing from finite to continuous samples and vice versa?

Hello,
I have a problem which I'm trying to overcome: I have a measurement system consisting of an analog output and reading two analog inputs. I would like to run it continiously to monitor the current values (without saving the previous data), however, when I click something like a record button, I'd like to start a recording of a predefined period (like a finite samples measurement) and then restarting the monitoring without saving again.
Currently my measurement program is based on the examples "Continuous AO" and AI vis, and are made with continuous sample mode and while loops. How can I insert a record button?
I tried putting event handlers in the measurement loop, however it suspended the loop from running.
I attach a screenshot of my current measurement loop. (With the shift register I tried to read data, however I cannot get it out of the loop, until the loop is stopped)
Thank you in advance
Engage! using LV2012
Attachments:
question.png ‏81 KB

I have tried adopting something similar, however it doesn't work the way it should. (Or at least the way I think it should) Could you please help me ironing it out? I've seen some vis on the internet with queue-controlled (but only one-way) and tried adopting them.
The MainProgram vi is the app, with some settings (now limited to a signal file selection and channel settings). Then the data acquisition can be started by clicking the Start Acq button.
And here come my problems: first sometimes the queue starts, sometimes it doesn't (or at least it doesn't start the data acquisition). And the main point: I set the sample rate, yet it is acquired at a much-much slower rate (my signal has a period time of 4 seconds, yet it needs at least 20 seconds to get near finishing). And the strangest: sometimes, mostly after some time (about 1-2 min) it hangs and does nothing with the daq (yet labview seems responsive, just my program hangs somewhere).
So now only the controlled acquisition is in the problem and first I don't care about forwarding the data for analysis and saving. (That seems to be the smaller problem).
What am I doing wrong? Thanks for your help.
I attach all the files. (MainProgram is the app itself, MY.SIGNAL is the signal file I want to output.) I use a USB-6211 device. (at work a physical one, at home a simulated one).
Engage! using LV2012
Attachments:
queued_daq.zip ‏366 KB

Finite planning in planning board

Hi Guys,
Sorry to ask these basic question. But please clarify me here.
1) As per SAP,we have Find slot, insert and squeeze in operations under finite scheduling.Now letz say our resource capacity is 100% and then have an order on 25.05.2014 which consumes only 40% capacity, it is finite scheduling (find slot), if an another order comes on same day which consumes only another 40% capacity, being finite scheduling where the second order be placed.
Will it place after the first order to get the slot or along with same first order saying it has the capacity.
How it will be for insert operation and squeeze in operation.
How PPDS planning look for the capacity of the resources?Is finite scheduling(Find slot, insert and squeeze in operations) work only with single-mixed resources?
2) As per standard SAP how PPDS will plan- Is it finite scheduling or infinite scheduling ?
Thanks,
Prash

Hi Prasanth,
Planning Heuristics like SAP_PP_002 plans infinitely based on strategy setting inside Heuristics. If you change strategy setting inside heuristics to finite scheduling mode it will plan finitely provided finite scheduling indicator is checked in resource.
Regarding finite capacity settings as time con. or bucket decides whether you will plan bucket oriened finite planning or normal. Bucket oriented is genrally used in case of block planning with capable to promise scenario.
As per best practice you should have planning run with infinite planning followed by schedulinhg heuristics or optimizer to achive finite plan.
Regards,
Santosh

HOW TO GENERATE FINITE AND CONTINUOUS PULSE TRAIN WITH USB6216 AT THE SAME TIME?

Hello.
I am using a USB6216 DAQ and need to generate a 20 kHz signal using the
ct0 output and at the same time I need to generate a finite number of
pulses, say 9, on a software trigger using the second counter output
ct1.
Currently, I have two VIs that can do this separately, but when I want
to integrate these into one single VI y get an error in the finite
pulse train for ct1 that indicates that the requested task is already
reserved. I am thinking this has to do with the fact that maybe both
types of task use the same timebase but I have not found the way to
solve this problem.
Any help would be very much appreciated.
Thank you.
Sincerely
JSL

Hello.
If anybody is interested, the problem is solved.
There is no resource confilct if I generate the 20 kHz continuous pulse
signal using the frequency out terminal, and this way I can use both of
my counters as I please with no problems.
It's kind of fun to answer one's own questions...
Sincerely
JSL

With DAQmx, how to use AO start trigger for AO/AI synchronization with finite AI sampling

I am a new user to DAQmx and I am trying to synchronize AI (finite samples) with AO in LabVIEW 7.1 using a PCI 6229 card. I want to generate a finite waveform (AO) and, subsequently, collect a finite number of voltage samples (AI). I would like to repeat the AO-AI cycles in a while loop.
Alternatively, I could use an infinite AO generation and collect finite number of voltage samples on AI but always exactly at the same spot of the AO buffer.
Using traditional DAQ and a 6024E card, I used a counter triggered by AO start trigger signal (example attached). I have problems with translating this example into DAQmx.
Please help!
Ruber
Attachments:
AIAODelay_traditional_Eseries.vi ‏155 KB

Lesley,
Thank you very much for your suggestion. Late last night I actually tried a to use AI start trigger instead of AO start trigger and it worked (since I tried the AI & AO to start simultaneously, it does not matter what triggers what), even in the loop. The devil is in details, as I had to carefully wire the number of data points and what to place inside/outside the loop.
The problem with shared clock is that I need to sample the AI and AO at different rates but using AO and AI clock separately did not seem to affect the performance.
I still want to try to use the AO start trigger (as you suggest) because I would like to delay the AI by a few ms from the AO. Is there a simple way to to that?
I suppose, switching from traditional DAQ to DAQmx requires your brain to be rewired - after playing with it for a couple of days and nights I developed a "feeling" for it. One of the differences was that, in order to use this example in the loop, one has to use 'stop task' inside and 'clear task' outside the loop.
Thanks again!
Radek Uberna

Finite pulse-train generation with variable time lapses with NiDAQmx

Being a newby in Labview and NiDAQmx, I find it tedious to program the application I need to drive my experiment : I want to generate a finite pulse train, with variable delays between two consecutive pulses. These delays are known before the experiment starts, summurized in a table (element 0 decribes the time lapse between pulse 0 and 1, element 1 between pulse 1 and 2 ...). I would like to use NiDAQmx to program this. I had in mind the following scheme : two counters, first one counting time between pulses, the second one generating the pulse once "counter one" has finished his job. What I don't figure out is how to reprogram "counter one"'s register, without introducing unwanted delays in the time
sequence of my finite pulse train. I am using a 6052E DAQ, and I want to generate delays in a same pulse train ranging from 1 microsecond up to 20 seconds.
Thank you for ANY help :-)

Hello !
Well, I will try to be more precise while answering your questions. But first let me thank you very much for your help : your comments, questions and remarks are very helpful to help me shape my project, as you shed light on particular problems I strictly had no idea before !
1) I can certainly get on well with digital output as my flash device is triggered by TTL signals.
2) The lighting device is home-made, and I think it will be better for my needs to produce light throughout the duration of the input at the “on” level. In any case it will be driven by TTL-like signals. The intensity is manually set, so no analog control is required.
3) I will use Labview to collect the experimental data. The signal will be sampled during the light pulse : the rising edge of the TTL-like output signal will trigger both the lighting device and the data acquisition, the latter being stopped on the falling edge. The light emitted by the lighting device is called a “probe” for the following reasons : the photons are absorbed by the photosynthetic sample and “immediately” re-emitted at a longer wavelength. A photodiode acts as a signal transducer, and I monitor the intensity of this fluorescence. Knowing precisely when light pulses occurred after the initial start excitation (which is also a brief pulse of light but of a much greater intensity than the “probe” light) and the intensity of light emitted during theses pulses, I can reconstruct the kinetic of fluorescence decay. This kinetic reflects the behaviour of my biological sample. Thus no continuous acquisition is required as between two light pulses there is nothing to monitor. And all the half-time reaction are timed relative to the same “start” excitation as they reflect a jump sequence of an electron extracted by the “start” excitation : first jumps are quick ones (half-time in the 10 �s range) and last jumps are slow ones (half-time in the 1 s range). With respect to these kinetics, I would like a 1 �s precision. If not achievable, I could skip the quickest jump (but it would be a pity) and focus on the second one which has a 10 ms half-time reaction and a 100 �s precision would then be enough. But as we say in French : “Qui peut le plus, peut le moins !” (roughly meaning that when you can achieve the best, you easily can do the least). This precision relates to the position of one flash with respect to the others. I don’t need to be very precise on the duration of each individual light pulse : a typical value is 100 �s duration, but I can get on well with 90 �s or 110 �s, my data being an average of the light intensity emitted during the light pulse). All I want to know precisely is when it is fired.
4) Concerning the hardware, I already have a NI 6052E DAQ board, and unfortunately my laboratory cannot allow me to spend more money on this. I also have a fast acquisition board (IMTEC T3012) I intended to use to acquire my photodiode signal in place of the 6052E A/D converter. It has an old Labview driver, and I managed to upgrade it to suit my needs. It has an onboard segmented memory and can keep track precisely (it has a 60 MHz sample clock) of a trigger event. I am wondering if I can overcome the timing precision issue with this board, knowing that I strictly don’t care that flash n�1 is triggered at (t0 + 10 �s) or (t0 + 11 �s), provided that I know it, allowing me to place precisely my data point on the time scale. I can program the number of memory segments (i.e. the number of light pulses) and each one is filled with data coming from the photodiode upon receiving the rising edge triggering the light pulse. The precise date at which each triggered is received is stored in the board memory, allowing time reconstruction.
I do hope this is much clearer than my previous attempts ! Believe me, it is quite hard to leave biology for a while and enter the cryptic world of data acquisition !
Gritche

Need to unreserve a counter in a finite pulse train generation

Hi. Let´s introduce my application first: I´m trying to generate a N-pulse train with the M series PCI-6221, in order to achieve a high frequency clock for an SSI transducer. That´s why i can´t use a software generation (because of the high frequency) and i have to use a finite pulse train. Besides, I would need to use another counter for a variable and finite count (but not simultaneously). The problem is that, as i think i have understood, this finite pulse train involves the two counters working together, so I can´t programm another task with that resources.
My question is, Is there any way to do the finite pulse train generation, unreserve the counters, wait for a finite count to finish and so on?
Thanks.

Hello,
My knowledges tell me that you need two counter to generate a finite pulse train.
The first counter generates a pulsed of desired width and the second counter generates the pulse train which is gated by the pulse of the first counter (Counter 0=Pulse Generation, Counter 1=Pulse train generation).
However, the finite pulse train generation and the continuous pulse train generation seem similar. The key difference is the generation mode from continuous to finite and the use fo a DAQmx Wait Until Done vi instead of a loop to monitor user input. From a point of view of the hardware there is a difference between the two. Continuous pulse train generation requires only 1 COUNTER.
Maybe you can try with a continuous pulse train generation and with this method you have another counter to do a finite count.
Regards
DiegoM.

How to change the frequency of a finite/continuous pulse train in the program?

Hello!...
I am trying to modify the Finite pulse train vi example to change the frequency with respect of a ratio (1:2) of the data of a spreadsheet file as they are read one by one.
My aim is to get the pulse train to clock a stepper motor controller, in such way that the speed of the motor increases when the data of the spreadsheet increases and vice-versa.
I think that if I want to get the clock to change its speed, I must change the frequency and if I want it to increase/decrease like the data in the spreadsheet, I must tell the frequency that the data is increasing or decreasing in value.
Obviously the program must do it while it is running
Can anyone see wh
ere I have gone wrong and/or give any suggestions?
I have attached my vi and the spreadsheet file.
Thanks
Tiano
Attachments:
My_VI.vi ‏99 KB
wave.txt ‏18 KB

Tiano,
Try to build the pieces of the program separately. Get a VI running that reads the spreadsheet and reports the data in it sequentially in an indicator (forget about the pulse generation at this time). This indicator will be wired to the frequency input of the pulse generator VI.
You have read the data and have a transposed array. Now you must learn to use the Index Array function in a For Loop to extract the data sequentially. You will wire the increment output [i] of the For Loop into Index Array to shift from one data point to the next.
You have a For Loop with no constant wired to [N] to tell it how many times to run. If you use Array Size to extract the number of entries in the spreadsheet data, this can be the constan
t that tells the For Loop how many times to run.
You are using the Tab Control in a way I have never seen before (I don't think it will work this way either. Tab Control is for presenting and hiding controls, indicators, labels, etc. on the front panel, before running the VI. They are not used to control the program functionality itself. Typically you would use a Boolean to choose between 2 options for a Case Structure.
You can also change the path constant which selects the spreadsheet file into a control. This would allow you to browse for any file you want and eleiminate the need for the Case Structure altogether.
Mike

No reqmts/caps exists or not relevant to finite shceduling

Hi All,
I am getting above warning message if click on capacity tab in process order.
I have maintauned finite scheduling tick all reources in which is applicalbel for this process order.
also i am getting information message Capacity availability: Capacity available work centers .Please help me out.
Regards
Sailendra

Hi
Check whther you have maintained the tick mark against Generate capacity reqmts for the your
detailed scheduling in the txn ;OPU3 for the combination of Plant , order type , prod schud.
CHECK THIS SAP help:
Indicator: Generate capacity reqmts (detailed planning)
The selection determines that capacity requirements are generated for detailed planning.
Dependencies
If you set the CapReqmnts indicator and the Scheduling indicator is set, capacity requirements are generated for the operations on the scheduled operation dates.
If you set the CapReqmnts indicator and the Scheduling indicator is not set, capacity requirements for the operations are generated for the complete producion period of the order.
Edited by: raj on Jun 9, 2009 1:11 PM

Delayed retriggerable finite pulse train

Hi there,
I'm trying to create a delayed retriggerable finite pulse train on a USB-6251 (2 counters). I just read an old thread on this problem and I got it to work.
However, I'm having this one small annoying issue:
I want to send a finite pulse train (3 pulses) at 1Hz
The trigger has a period of 3seconds (0.333333Hz)
My initial delay is 0.1s
This results in the following :
first 3 seconds : perfect 0.1s delay, 3 pulses at 1Hz
second 3 sec : nothing
third 3 sec : perfect 0.1s delay, 3 pulses at 1Hz
and so on
I reckon this is because the counter that is gating the continuous pulses is not finished yet with his pulse and therefore does not "see" the new rising edge of the trigger.
Is there a way I could solve this?
I know I could just use the first trigger and send 150 pulses or so at 1Hz. That's what I would do if I was very confident in the accuracy of the 3s period of the trigger, but I'm not. And since it is very important the timing is accurate after that trigger, I think I will induce to much error in the timing that way.
Any ideas?
Cheers,
Tom

Sorry for boosting this thread, but I just noticed something in the program Alan suggested : Delayed_Retriggerable_Finite_Pulse_Train.vi while checking its output on a scope:
If you set an initial delay, the pulse train actually starts after 2 times that delay time after the initial trigger. I can't seem to find where this factor 2 is coming from.

Retriggerable finite pulse train

I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continueous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on between pulse trains, when it should be turned off. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. I use the ActualPeriod of the first re-triggerable pulse to ensure the pulse train ends correctly within window of the first re-triggerable pulse, but it seem to wander. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem. I may have to use a single re-triggerable pulse instead of a re-triggerable pulse train as this work correctly every time. However, multiple pulses creates a finer mist from a fuel injector and is the correct why to modulate a fuel injector. The

CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

How do program 3 independent finite pulse train generators from 3 counter pairs

I need to drive a 3-axis piezo leadscrew friction type motor by finite train of pulses from a PCI-6602.How do I specify the counter pairs in my code with out any one counter conflicting with the others?
Bernardino Jerez Buenaobra
Senior Test and Systems Development Engineer
Test and Systems Development Group
Integrated Microelectronics Inc.- Philippines
Telephone:+632772-4941-43
Fax/Data: +632772-4944
URL: http://www.imiphil.com/our_location.html
email: [email protected]

This scheme (and the examples) works fine when you want finite generation done in sequence, but seems not to work with when they are done independently and in synchronously run in parallel fashion.
Berns B.
Bernardino Jerez Buenaobra
Senior Test and Systems Development Engineer
Test and Systems Development Group
Integrated Microelectronics Inc.- Philippines
Telephone:+632772-4941-43
Fax/Data: +632772-4944
URL: http://www.imiphil.com/our_location.html
email: [email protected]
Attachments:
Mutliaxis_test_drive_version_0.vi ‏85 KB
NF8096Exercise.vi ‏206 KB

What sets no.of pulses in 'finite pulse train' intermediate vi

I want to know how the 'finite pulse train' intermediate vi works. from the VI info I find that counter n generates a continuous clock pulse and is gated by a gating signal coming from counetr n-1. but when I actually run this vi, I find that the counter 2 does not generate a continuous clock pulse and the gating signal is also not used at all for this vi.
I also find that the 'no. of pulses' input does not linearly correspond to the no. of pulses but to the speed of the motor as well. ( I am using the counter to generate a clock train that is used to drive a motor). Nevertheless, when I measure the freq from the output of the counter n , I still find it be to the same as the clock freq that I input thro
ugh my program (and hence independant of step pulses). This is surprising because the speed of the motor changes at constant freq clock trian from counter n.
can anyone tell me whats going on here ?
thanks very much,
Lalitha.

Hello Filipe,
well, here's what I find when I run the vi. I am using a PC-TIO-10 board- so I have given the signals with ref to the pin outputs of this board as well.
I do not get a continuous clock pulse at the output of counter 'n' when I run the program with the gate of counter 'n' tied high all the time.
for instance, I tied gate 2 (pin 5) to high all the time and ran the program. I would have expected a continuous clock pulse to be generated at out 2 (pin 6 ). but only a finite clock pulse whose freq corresponded to the input clock freq was output at OUT 2.
then I tied gate 2 to low and repeated the run- again a finite clock pulse was obtained at OUT 2. It behaved as if the gating signal at gate 2 did not matter at all. All this was while
keeping the gate mode at 'count while high' and the pulse polarity at high (default values).
finally, I also wired out 1 (3) to gate 2 (5) and ran the vi. this is exactly the way the I/O connections should be made as per the vi info. but there was no output at OUT 2 (6) even though the gating signal was observed at OUT 1 and therfore tied to gate 2.
thus my VI is not generating a continous clock pulse at the counter 'n' OUT pin - I always get only a finite clock train and this is regardless of whether the gate of the counter 'n' is tied to high/ low/ OUT of previous counter.
why does this happen ?
thank you
Lalitha.

How do you create a finite pulse train using a FP-CTR-502?

I have recently replaced my FP-PG-522 module with a FP-CTR-502 module, to achieve higher output frequencies (FP-PG-522 max output freq is 5kHz, wheras the FP-CTR-502 max output freq is 16 kHz).
I need to be able to generate a finite pulse train. Has anybody created a finite pulse train using a FP-CTR-502 module before? I have started to look into it, but my ideas so far have been complicated (compared to doing it in a PG module).
Any tips on this would be much appreciated.
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au
Solved!
Go to Solution.

I can answer this question myself!
The answer is in the *OLD* version (July 2000) of the operator's manual for the FP-CTR-502. For some reason, this has been removed from the latest version (June 2003).
See page 11 of this link for more information:
http://www.ni.com/pdf/manuals/322660a.pdf
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au

Finite cheduling

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