FPGA Device I/O

How can I get an FPGA I/O Icon on the Function Pallet. I'm using a cRIO.

Hai,
Its easy.
Just check out the attachments.
Navigate to programming>>FPGA then pick the FPGA IO node place it on the block diagram.
or just type "FPGA IO" in search of the functions pallete that will lead directly to the pallete.
With best regards
JK
With regards,
JK
(Certified LabVIEW Developer)
Give Kudos for Good Answers, and Mark it a solution if your problem is solved.
Attachments:
fpga io.JPG ‏26 KB
fpga io node.JPG ‏13 KB

Similar Messages

UDEV rules for Xilinx FPGA devices

I recently purchased a Digilent Nexys3 FPGA board with a Xilinx Spartan 5 FPGA on it. I finally got around to finding some time to using it, and setting up the development environment under Arch linux.
After spending ages reading around about various problems and workarounds, I finally managed to get Xilinx ISE Webpack installed and working, as well as Digilent Adept software for downloading the designs to the development board. One issue still remains though. I am unable to download the designs to the FPGA as a normal user, but only as root.
I'm pretty sure this is a udev rules problem. Digilent supplies a rules file (attached below) which is supposed to grant permissions to all users to access the FPGA devices over USB. I placed this rule file under /etc/udev/rules.d, but I am still unable to access the devices as normal user due to the following error:
$ djtgcfg enum
libusb couldn't open USB device /dev/bus/usb/001/003: Permission Denied.
libusb requires write access to USB device nodes.
$
I believe that udev rules syntax changed since the last time I had a look at it, so maybe the supplied rules file still uses the old syntax? Any suggestions to fixing this rules file (attached below)?
# 52-digilent-usb.rules -- UDEV rules for Digilent USB Devices #
# Author: MTA #
# Copyright 2010 Digilent Inc. #
# File Description: #
# This file contains the rules used by UDEV when creating entries for #
# Digilent USB devices. In order for Digilent's shared libraries and #
# applications to access these devices without root privalages it is #
# necessary for UDEV to create entries for which all users have read #
# and write permission. #
# Usage: #
# Copy this file to "/etc/udev/rules.d/" and execute #
# "/sbin/udevcontrol reload_rules" as root. This only needs to be done #
# immediately after installation. Each time you reboot your system the #
# rules are automatically loaded by UDEV. #
# Revision History: #
# 04/15/2010(MTA): created #
# 02/28/2011(MTA): modified to support FTDI based devices #
# Create "/dev" entries for Digilent device's with read and write
# permission granted to all users.
SYSFS{idVendor}=="1443", MODE="666"
ACTION=="add", SYSFS{idVendor}=="0403", SYSFS{manufacturer}=="Digilent", MODE="666", RUN+="/usr/local/sbin/dftdrvdtch %s{busnum} %s{devnum}"
# The following rules (if present) cause UDEV to ignore all UEVENTS for
# which the subsystem is "usb_endpoint" and the action is "add" or
# "remove". These rules are necessary to work around what appears to be a
# bug in the Kernel used by Red Hat Enterprise Linux 5/CentOS 5. The Kernel
# sends UEVENTS to remove and then add entries for the endpoints of a USB
# device in "/dev" each time a process releases an interface. This occurs
# each time a data transaction occurs. When an FPGA is configured or flash
# device is written a large number of transactions take place. If the
# following lines are commented out then UDEV will be overloaded for a long
# period of time while it tries to process the massive number of UEVENTS it
# receives from the kernel. Please note that this work around only applies
# to systems running RHEL5 or CentOS 5 and as a result the rules will only
# be present on those systems.
Thanks!
-Igor
Last edited by UQ-igor (2011-12-24 03:56:10)

Try this
Use ATTR or ATTRS.
-SYSFS{idVendor}=="1443", MODE="666"
-ACTION=="add", SYSFS{idVendor}=="0403", SYSFS{manufacturer}=="Digilent", MODE="666", RUN+="/usr/sbin/dftdrvdtch %s{busnum} %s{devnum}"
+ATTRS{idVendor}=="1443", MODE="666"
+ACTION=="add", ATTRS{idVendor}=="0403", ATTRS{manufacturer}=="Digilent", MODE="666", RUN+="/usr/sbin/dftdrvdtch %s{busnum} %s{devnum}"
+ATTR{idVendor}=="1443", MODE="666"
+ACTION=="add", ATTR{idVendor}=="0403", ATTR{manufacturer}=="Digilent", MODE="666", RUN+="/usr/sbin/dftdrvdtch %s{busnum} %s{devnum}"

Why is "FPGA device emulator" not an option in my target list?

I have the LabVIEW RT module and the FPGA module installed.
(LabVIEW 7.1)
I have developed several VI's for the cRIO, but one thing has always stumped me: On my targets list, I have "Windows", then I have "compile only xxxx" where xxxx is my FPGA device, then I have "RT:IP-address" and also "VISA::FPGA" option, but, as mentioned in the topic, I do not have a "emulator" option in the target list.
Now, up until today, that has not been to much of a problem, but now, I have a bug in my VHDL code, and since I cant emulate, I cant use probes and every change I make forces me to do a 30+ minute re-compilation. To make it worse, I do not have enough room left on my device to have "Indicators" for all signals I would like to look at, so debugging my code is -A PAIN-.
If anyone could help me with tips as to how to get the "emulator" option, I would be grateful.
System specs:
Win XP home (SP2 with all the latest updates)
LabVIEW 7.1
LabVIEW RT ETS
LabVIEW FPGA (1.1?)
Pentium 4, 1.6GHz
768MB RAM.
Project Engineer
LabVIEW 2009
Run LabVIEW on WinXP and Vista system.
Used LabVIEW since May 2005
Certifications: CLD and CPI certified
Currently employed.

Hello,
I am glad that targeting LabVIEW for Windows does the trick. About the Digital Input, you are right. All IO is simulated when targeting LabVIEW for Windows. So what you get is only random data generated by LabVIEW. As soon as you target to the FPGA, it will talk to the IO and then you will have true data.
Ricardo S.
National Instruments.

An error occurred downloading the VI to the FPGA device.

Hello,
So I'm trying to download a VI to my FPGA and I get the following error every time. Could you help me with this? Does anyone know how to solve this?
"An error occurred downloading the VI to the FPGA device. Verify that the target is connected and powered and that the resource of the target is properly configured."
Thanks

Hi,
Please verify that:
You have installed FPGA, NI RIO, LabVIEW Relatime ALL in the SAME VERSION!
Do you see your Target in NI MAX? Here you can verify the software version.
Can you connect your Target in the LabVIEW Project, by rightclicking on it, and connect? (some useful steps of troubleshooting are here:
Why Can I Not Connect to my PXI RealTime (RT) Target on the Network? http://digital.ni.com/public.nsf/allkb/24D16468DE8838B2862568E200746D7E
If you checked that the best way is to start over:
verify you can connect to your target by addressing the target via webserver
if not follow: http://www.ni.com/gettingstarted/installsoftware/compactrio.htm
if you can connect go ahead to formating the target WITHOUT resetting the network information.
When you were able to start your programm once, and now you can no more connect to it, it might be a good idea to check out, if your targetsystem has met the CPU limit of over 75% usage.

Use shared variables with FPGA device on Host PC

Hi all I am having a frustrating problem. I am trying to use shared
variables linked to a cRIO 9012. The shared variables were created and
then written to in a RT vi. is there any way I can assign locations to
these not within a RT vi. I altimately need to run the Host vi on a
TPC-2512 touch panel computer and I can't run a RT application on that. I
just need the variables to update without the RT vi running and I can't
figure out how to do that, if its even possible. Here is what I have so
far. Thank you in advance for your help.
Attachments:
PumpMonitoringDevice.zip ‏2083 KB

Adam:
You may be able to use arrays to speed up your program, but bear in mind that the TPC is pretty much guaranteed to be slower than your computer (as it's likely to have lower system specs).
You'll want to use the array manipulation functions to combine and retrieve your data (most useful will likely be "Build Array" and "Index Array," see context/LabVIEW help for more details). Once you have the data in an array, you can likely pass it through a shared variable configured for an array datatype.
I'm not sure if/how much of a speed boost it will give you, but I think it's definitely worth trying. If you're not sure about the speed, try simply cutting your variable count in half and see what kind of speed increase you get with the same amount of code but fewer variable values being transmitted through your network connection.
Good luck!
Caleb Harris
National Instruments | Mechanical Engineer | http://www.ni.com/support

Device drive of lab view fpga 2013 for Spartan 3E FPGA

Hi NI
I has get labview 2013
but I need FPGA device drive of Spartan 3E
can NI release it for us !!!!!!!!!!!!
best regards
hi ?Q>

T-REX$ wrote:
Hey mangood,
There currently is no support for the Spartan3E board in LabVIEW FPGA 2013, and I am not aware of any plan for developing support in the near future. Sorry for the bad news...
DEAR
i have lab view 2012 and it has device drvie for spartan FPGA
only one year
may be can NI do this its simple
thank
hi ?Q>

FPGA memory limitation

Hi...
I have tried to use more than 2 MB memory (using memory blocks) on FPGA. During compilation Xilinx tool chain generated error "AR #21955"....which is explained as memory limitation (in xilinx website). Can't we create memory blocks of more than 2 MB?? (or) all memory blocks size in a vi should not cross 2 MB??. I need to create arbitrary wave forms of milli/micro second precision for some minutes......so i need many no. of points to get required waveform....Is there any way to achive it....when I transfered each point from a RT vi (not on FPGA) it takes more time (to transfer data from RT vi to FPGA vi for every iteration).
Thank you,
Cheers,
Ravinder

The size of the memory blocks you can allocate in the project and use in your FPGA VI is limited by the size of the memory available on your FPGA device. This memory is in the range of 80-192 kB depending on which FPGA device you are using. Please check the data sheet or manual for your device for details.
http://sine.ni.com/manuals/
So unfortunately you will not be able to store the complete waveform on the FPGA device.
Your best option is to stream the waveform from host memory to the FPGA device using DMA and generate the data from the DMA FIFO in the FPGA VI.
Message Edited by Christian L on 08-06-2008 06:24 PM
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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New "Targets and Devices..." dialog does not open in Project window

Hi I am trying to add an FPGA device in my project, however when I right click on Project, and go to New -> Targets and Devices...It appears as though it is busy (the mouse icon becomes the hourglass) and after while it just goes back to normal and nothing seems to happen. I have an FPGA device installed which is the RIO card PXI-7831R, and the devices seems to be working fine. When opening a project that already contains it as a device, it is displayed fine. Its just the dialog to add new devices and targets does not appear. I have tried Repairing NI Labview 8.0 and NI Labview FPGA Module, but the problem still exists. I would appreciate if anyone has any idea as to why this is happening and how to resolve it. Thanks!

Hi Kewsvnet
So you have tried the device on another machine and it works fine, is it only on a specific machine that this issue is occuring on? I think I misunderstood the issue yesterday, am I right in understanding that when you click on 'New Devices and Targets' absoloutely nothing happens apart from the 'hour-glass' appearing for a while? If this is the case it maybe the case that LabVIEW may have become corrupted in some manner. Repairing it will not solve an issue like this. What you should try is to force LabVIEW to create a new .ini file, which holds all the configuration settings. To do this you need to rename the .ini file so that when LabVIEW starts it will detect no .ini file an create a new one.
The .ini file can be located via C:\Program Files\National Instruments\LabVIEW 8.0\ LabVIEW Configuration Settings (it is a file size in the range of 2Kb - 10Kb)
You need to rename this file 'LabVIEW Backup', then attempt to restart LabVIEW and a new project and try to add a target.
Let me know how you get on
Kindest Regards
YatinM
Applications Engineer
NIUK & Ireland

FPGA Poission Random Number

Hello,
I have Xilinix Virtex 5 FPGA and i want to implement poisson random number generator.
FPGA works at 100 MHz clock and at every cycle it should calculate poisson random number. Mean value of poisson distribution can change at every clock cycle. I want to make random time pulse generator with possion distribution. Pulse rate can vary between 1 and 1 billion pulses per second.
How i can make this generator? Please, help

b,
There are two kinds of randomn number generators that are commonly implemented in a FPGA device: a true random number generator (very hard to do), and a pseudo random number generator (trival to do).
The pseudo random generator is done using linear feedback shift registers, and its statistics are well understood, and do not vary (in fact, the sequence repeats depending on the length of the LFSR).
Attached is a form of true random number generator.
To get a specific distribution (e.g. Poisson) you would need to verify and [perhaps filter the genberated numbers.
Poisson being as close to radomn as possible (for example, radioactive decay times are Poisson distributed), a true randomn number generator is where I would start (the attachment).

FPGA output different to emulator

I've written a simple vi that outputs a sine wave using the FPGA sine generator. This passes through a half-wave rectifier setup (via a SCB-68 connector block) and back into the FPGA. When I set the execution target to the FPGA emulator the vi works perfectly. A full sine wave is displayed on one wave-chart, and a half wave on other. However, when I target the FPGA device and compile and download the vi, the output turns into what appears to be random noise. Both wave-charts show nothing like a sine wave. Whats going on?
Cheers,
Rob.

Actually i've just found the following in a help file, i'll give it a go...
Sine Generator Details
If you target an FPGA device emulator, the Sine Generator VI outputs every point of the generated sine wave, regardless of the rate at which LabVIEW calls the VI. To produce the same data while targeting an FPGA device emulator as when targeting an FPGA device, change phase increment to take into account the rate at which the FPGA VI calls the Sine Generator VI. The following equation determines the correction for using an FPGA device emulator.
phase increment (emulation) = phase increment (FPGA) * FPGA loop time (ticks)

Fpga data persistence volatility

I was just wondering about the persistence/volatility of the various memory methods after cycling power to LabVIEW FPGA Devices? Is it possible to ensure that data persists after cycling power?
Jordan McBain, PhD
LabVIEW Controls Engineer
Revolutionary Engineering
Solved!
Go to Solution.

There aren't that many memory techniques. You can store data on the FPGA either in logic gates, or in RAM. Both of those are volatile - they lose their contents when not powered. Some FPGA boards do have onboard non-volatile FLASH, but that is generally used to store a bitfile to be loaded on power-up. I do not know if it is possible for the FPGA to access the FLASH while running, but if it is you would need to write custom low-level (non-LabVIEW) code to do it, as there are no built-in functions that allow it.

Rt / how can a fpga-bitfile be exchanged without recompile the rtexe?

Hello to all,
maybe someone of you knows the trick:
my program have two parts, one is running on RT-OS (LabView RT/PharLap) the other part is on a FPGA. For programming I'm using LV 8.5.1.
In the VI (on RT) which calls the FPGA, is a static path-reference on the bitfile. Idea of this was that the bitfile is dynamically loaded by every start of the RT and when there are bugfixes to do in the FPGA-code, then this could be done with an simple exchange of the bitfile (which I can send to the customer and he replaces then byself the file per FTP).
In fact replacing of the bitfile does not have any effect, it seems that the bitfile is integrated in the RTexe and so cannot be exchanged on harddisk. Only way to replace the bitfile seems to recompile the RTexe with the new bitfile.
Does anyone knows how this can be solved? Or is there no way to do so that a bitfile is loaded at runtime (as a file and not integrated in RTexe)?
Or is this maybe because the VI which calls the bitfile, is forced to be part of the compiled RTexe (build options)?
Greets,
Lars

Hi Lars,
as far as I know there are 2 ways to dynamically download a bitfile to an FPGA
device.
1. Using the NI-RIO driver (available at: http://joule.ni.com/nidu/cds/view/p/id/993/lang/en)
When you install the NI-RIO driver, the RIO Device Setup utility is installed,
which allows you to download bitfiles to the flash memory of your FPGA device.
After that when the device is reset or powerup, the device itself can load and
start this new bitfile. Just make sure that the option "Autoload VI on
device powerup" or "Autoload VI on device reboot" is set
accordingly under Device Settings in the RIO Device Setup utility. Change
these options of the device so that the bitfile is loaded on a reset or power
loss, then reset or cycle the power for the device.
2. Using the FPGA Target System Replication utility as discussed under: http://zone.ni.com/devzone/cda/tut/p/id/6465
With the help of the VIs included in this utility (http://digital.ni.com/public.nsf/websearch/AF4FF0C65AF31B4348257337006A144A?OpenDocument) you can basically set the same options and select a bitfile similar to the RIO
Device Setup utility of the NIO-RIO driver. Similar to the RIO Device Setup
utility you can download your bitfile to the flash memory of your FPGA and then
reset or power cycle your device.
I hope this information helps you.
Best regards,
Balazs

RT Host VI does not communicate with FPGA VI with PID Discrete controller

Hi. I am using LV 7.1 RT with PXI 7831R. While developing an application with a PID controller in the FPGA vi, I have run into the following problem:
1. After a successful FPGA compile, the code runs directly on the FPGA device and the PID controller works fine.
2. After I switch to the RT and run the host vi, it shows no activity from the FPGA vi. I look at the while loop count of the FPGA (indicator named 'FPGA-count' in the snaps below)) and it shows 'zero'. I have refreshed the FPGA vi reference but to no avail.
3. If i take out the PID related stuff from the FPGA vi, then the Host vi to FPGA communication works.
I have attached snaps of a simplified version of the fpga and RT vi's. If anyone can help, that would be greatly appreciated.
I also read that the PID control toolkit needs to be installed. It is installed on the host computer and shows in Automation explorer under LV 7.1. Does it need to be installed on the remote machine that is the RT controller as well. if so, then how to do that.
Thanks
Attachments:
RT-frt panel.JPG ‏38 KB
fpga-block.jpg ‏39 KB
RT-block.JPG ‏35 KB

It seems like the FPGA is not running for some reason when you are running the RT VI. Without having the actual VIs to look at I can only make a few guesses why.
On the Open FPGA VI Reference make sure the option is set to Open and Run, not just Open. Right click on the node to check this option.
On the RT VI, make sure that stop-FPGA is False before you start.
On the FPGA VI, make sure that the default value for stop-FPGA is set to False.
In the RT VI check the error cluster passed to the loop to make sure that there are not errors and the FPGA VI is actually running.
If you are using the PID function on the FPGA, you do not need any additional SW installed on the RT controller. If you are using the PID function in LV RT then you do need to install the PID toolkit on the RT controller. This is done from MAX (Measurement and Automation Explorer) using the Install Software option for the controller.
Christian Loew, CLA
Principal Systems Engineer, National Instruments
Please tip your answer providers with kudos.
Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
or for use in hazardous environments. You assume all risks for use of the Code and use of the Code is subject
to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense

CPU accessible registers in LabView FlexRIO FPGA

Howdy folks, I am wondering if it's possible to get the following behaviors out of Labview. I'm thinking it's not.
System description: CVI application that communicates with PXIe FlexRIO via controls and indicators.
Problem: Designing to a CPU-FPGA interface specification which lists "registers" as a combination of read and read/write bit-fields.
Example:
According to the spec, there should be a 32-bit register. Bits 31:16 are read-only, and bits 15:0 are read/write, from the perspective of the CPU. In the labview world, I would just make a uint16 control, and a uint16 indicator and be done with it.
However, to meet the spec (written for traditional microprocessor buses), a 32-bit read to an address should read back the full contents of the 32-bitregister at that location (implemented as flops on the FPGA, with appropriate memory mapping within the FPGA device). Similarly a 32-bit write to an address should store values to that register (appropriately masking writes to bits 31:16 within the FPGA device).
Is there a way for me to have a single address (basically, a single labview block diagram component) that will let me accomplish this behavior? It looks to me like the only solution is to pack my registers with bit fields that are all read, or all read/write in order to fit in with the labview paradigm. That means the spec will have to go back and be re-written and re-approved.
Thanks in advance,
-J
Solved!
Go to Solution.

Nathand,
Here is the standard paradigm (some simplification):
1) C helper file that contains #defines that describe the memory map. things like BASE_ADDRESS, DEV1_OFFSET, DEV2_OFFSET, REGISTER_1_OFFSET. To get to a
2) C procedure which calls things like void setRegister(uint32 *memory, int device_offset, int register, uint32 new_data, uint32 write_mask). and uint32 getRegister(int base_address, int device_offset, int register).
3) If I want to write the value 0xABCD the upper 16 bits of a 32-bit register (register 5), to device #1, I would code:
main(){
setRegister( ptrMemory, 1, 5, 0xABCD0000, 0x11110000)
This would compute the PCIe address based on some equation like BASE_ADDRESS + DEV1_OFFSET+register_offset<<2 (byte addressed).
Suppose this gives us a 32-bit address of 0xC000_4000. We would issue a write across PCIe to address 0xC000_4000. The memory map in the FPGA is programmed such that a set of flops will latch the data in the PCIe write when write_enable = 1, and address 0xC000_4000 are both true. That completes the register write to the FPGA.
A similar thing occurs for a register read. In this case however, when read_enable = 1 and address = 0xC000_4000, the values held in that same set of flip flops is now written onto the PCIe as a transaction. The software application recieves the value and returns that value from the getRegister function.
In my example above, you notice that the same address on the PCIe is used for reading and writing. I am trying to understand if I can have software read AND write from the same address.
When you compile an FPGA, labview creates a (seemingly) arbitrary address translation for all CPU accessible structures, meaning FIFOs, controls and indicators. It assigns different addresses for every single item, and it may or may not keep the same address depending on whether any modifications were done to controls/indicators/fifos since last compile.
I am trying to understand how labview works, so that I can assess whether or not I can read/write from the same address. This matters, because if I can pack bit fields into registers more efficiently in the FPGA, that reduces the amount of functional tests to write and execute to verify the FPGA functionality.
So, a restatement of my original question: is there some mechanism with using controls indicators where both the FPGA AND the CPU can write to the same set of flipflops in the FPGA? If I use an indicator, the FPGA can write to the indicator but the CPU cannot. If I use a control, the CPU can write to the control, but the FPGA cannot. Is this correct?
-J

NI FPGA based programmed delay generator

Hello,
I am seeking for some suggestions from those working with degital delay generators.
We have a TTL trigger pulse train in which pulses are not equidistant in time (seperation between two pulses is not the same, it can be few ns to few microsecond), however, on average, the rate would be <2MHz. The pulses are 10-20ns width and 2.5V amplitude. From this, we want to generate 3-4 trigger pulse trains, which would be delayed with respect to the initial (input) pulse train by some arbitrary values (ns to few microsecond). However, the point is, we also want some trigger pulse trains in which only even number of triggers (or odd triggers) could be present. So in other words, we want to program the delay generator in such a way that one of the outputs could have only even or odd trigger pulses of the initial trigger pulse.
We first tried to look for available delay generator boxes and PCI delay generators. The problem is that they have insertion delay of typically 50ns or more. So in other words, the output triggers would be delayed from the initial trigger pulse not less than 50ns. Other, If we program them with labview, It seems the output response would be after few ms. These are quite large delays for us.
One such delay box manufecturing company suggested us to use FPGA based delay generators, as they say that these devices are having low insertion delays and quite fast programmable response. I looked in NI website for insertion delay and other parameters, but could not find these values. Pl. suggest whether FPGA based delay generators have low insertion time (<10-30ns) and if we program them, the output could be generated within ns response time?? As I am new with such devices, I would sppreciate if anyone could suggest about the possibilities to generated the delay sequences (even only or odd only triggers) using FPGA devices.
Thank you

MWM,
If you are planning to use the analog input I would recommend using the the 783x family of boards. They have analog inputs and they can provide the +/-10 v to the cRIO-9263 boards

FPGA Device I/O

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