How do i develop code in LabVIEW 7.1 for configuring and performing gated edge counting using NI-DAQmx

Hi,
My application requires DAQ counter channel to count the rising edge of the input signal connected to the source pin of the counter. This counting has to take place only when there is a high pulse in gate pin of the same counter.This can be developed easily using traditional daq vis.
Please let me know how to develop code using DAQ mx.
Thanks,
Sudha

There is an example that demontrates how to do this in DAQmx called "Count Digital Events-Pause Trig.vi".
gus....

Similar Messages

How to prevent BGP code 6 (Cease) subcode 6 (Other Configuration Change)

Can anyone tell How to prevent BGP code 6 (Cease) subcode 6 (Other Configuration Change) ?
We are facing frequent problem with this error. Please suggest how to stop this....
Note :- We are using BGP VPN between this peers.
Logs :
Date/Time : 2015-04-30 00:49:40+05:30
State : Up
Date/Time : 2015-04-30 00:39:05+05:30
State : Down
Error Code : 6(CEASE)
Error Subcode : 6(Other Configuration Change)
Notification : Send Notification
Date/Time : 2015-04-29 18:22:11+05:30
State : Up
Date/Time : 2015-04-29 18:21:39+05:30
State : Down
Error Code : 6(CEASE)
Error Subcode : 6(Other Configuration Change)
Notification : Send Notification

on the same dates you mean the same request are posted in IT2001? ie both full days?
Please clarify
usually the Time collision checks are followed only via posting using report rptarqpost and not while applying through portal in ESS
This is very strange you indicate
SO you need to check the basic tables first
You may need to check the collision.
Collisions Tables V_T554Y and V_554Y_B reaction indicators.
and V_T508A
able T582A set to time constraint of "Z
In backend Pa30 collision works like this
1) the logical collision, checks if there is an overlap in the validity
interval of the IT´s (begda, endda).
2) the physical collision, checks if there is an overlap in the time
interval of the IT's.
In the logical collision it is checked if there is an overlap in the
validity interval if at least one of the records is a full-day
( that is the case when you enter a Daily Work Schedule (DWS) )
So when one of the records has a DWS it is considered to be a full day
record and the logical collision is taken into consideration.
If instead you enter the only the time interval manually the records
are considered to be partial-day and the physical collision is
performed. In that case only the time interval is important.
So if the clock times are not entered the physical collision can not
take place.
The collision functionality is always based on clock times and dates,
never on the total nr of hours.
Edited by: Siddharth Rajora on Sep 21, 2011 4:57 PM

How do I get an iPad micro sim card for Austria and Italy? We purchased one for Germany, but it doesn't cover in Austria or Italy

How do I get an iPad micro sim card for Austria and Italy? We purchased one for Germany, but it doesn't cover in Austria or Italy

Compare the roaming charges from the German carrier with services like those:
http://www.abroadband.com
http://www.maxroam.com/Shop/Product/Detail.aspx?ProductId=787&cur=EUR
Otherwise buy a pre-paid micro-SIM card for the iPad in each country you visit.

How do I change my mouse to right click for copy and paste

How do I change my mouse to right click for copy and paste?

OK, what mouse are you using? Brand, model? Your right click should register as a right click unless that has been overridden by a preference pane. If your Mouse preference pane looks like this, your right click should be the equivalent of a control-left-click on a Mac.

I had a code to get logics pro for free and after it installed its asking me for a serial number does anyone know what to do from here.

I had a code to get logics pro for free and after it installed its asking me for a serial number but it never gave me one to put in, it just started downloading and then asked me. Does anyone know what to do from here.

I really don't think that is anywhere near on track.
Most likely the trial version was installed earlier, is that correct?

How do I switch my email account to cell for FaceTime and iMessage

How do I switch my email account to cell for FaceTime and iMessages?

I think you are asking how to use your phone number with FaceTime and Messages rather than an email address, but you must have an iPhone number not just any "cell" phone number.
Take a look at this.
iOS and OS X: Link your phone number and Apple ID for use with FaceTime and iMessage

My daughter received an I phone for Christmas and we set it up using my iTunes account. She just received an iPad and wants to set up her own iTunes account. How do we do that without lsing all of her content that she added to my iTunes account.

My daughter received an I phone for Christmas and we set it up using my iTunes account. She just received an iPad and wants to set up her own iTunes account. How do we do that without losing all of her content that she added to my iTunes account. I have home sharing on my account.

Welcome to the Apple Community.
If she creates her own iTunes account she can't use any protected content purchased under another account. She can play unprotected content synced from an iTunes library on a computer, but she can only download content from the cloud that is purchased under her account.
It's a pain I know, but the longer you put off the move, the worse the situation will become.

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

How to implement this code in labview?

How do implement this pseudo code in labview? Please keep in mind "a" and "c" in the code below ARE VARIABLES
for i =0 to i=maxvalue
if i <= a
output = output2
else if i > a AND i<=c
output = output2
else if i < c
output = output3
else i = d
output = output4
I understance i can use a case structures and modify the label, but i do not know how to make the label dependent on a variable value.
Thanks

Try an array of boudaries and use threshold array. See this old example:
Now just iterate over an array of values using a FOR loop.
LabVIEW Champion . Do more with less code and in less time .

Are there LabView VI's for accessing and writing data to a CDF?

I am currently trying to develop a data acquisition system using LabView to acquire the data and to write the data to a file in NSSDC's Common Data Format (CDF). The CDF distribution (Windows 2000) comes with a precompiled dll of the CDF library of functions. Unfortunately, LabView crashes when I try to use the Call Library Function node. I am confident that it is not a function prototype error, but it may be that the CDF library is not thread-safe.
Has anyone developed VIs for writing and accessing data in CDF format?
Does anyone know how I can determine why the Call Library Function node causes LabView to crash when it uses a particular dll? There are a host of reasons given in the "Using External Co
de" manual, but no apparant way of determining which one is the culprit.

Thank you for your response. Actually, I have solved the problem by recompiling the source code for the CDF distribution using the Cygwin development environment. Cygwin provides a unix C compiler and linker which can create Windows executables and dlls. After modifying the makefiles that came with the CDF distribution I was able to build the dll and then use the Call Library Module to access the CDF functions.
A note about this process: the linker that Cygwin exports both Windows-style and C-style functions when it creates the dll. Be carefull not to use functions that end in underscores from the CDF dll as C-style functions.
Also, I would like to point out that the current faliure method of the Call Library Module (i.e. crashing LabView) is not acceptable.
It would be much better if LabView would generate an error message or an error log entry in case of a dll failure. I would hope that this scenario would be a target goal for future development of LabView. The Call Library Module is an incredibly powerful tool in that opens up many avenues of development -- it deserves a better way diagnosing problems.

How do I set up a new phone number for messaging and facetime on my iPad?

My iPad has it's own phone number through Verizon. Before I knew this, I had already set up messages to use my iPhone number. Now I can't figure out how to set up the iPad phone number for messages and facetime on the iPad.

Are you trying to message another Apple device?
Using FaceTime http://support.apple.com/kb/ht4319
Troubleshooting FaceTime http://support.apple.com/kb/TS3367
The Complete Guide to FaceTime + iMessage: Setup, Use, and Troubleshooting
http://tinyurl.com/a7odey8
Troubleshooting FaceTime and iMessage activation
http://support.apple.com/kb/TS4268
Using FaceTime and iMessage behind a firewall
http://support.apple.com/kb/HT4245
iOS: About Messages
http://support.apple.com/kb/HT3529
Set up iMessage
http://www.apple.com/ca/ios/messages/
Troubleshooting Messages
http://support.apple.com/kb/TS2755
Setting Up Multiple iOS Devices for iMessage and Facetime
http://macmost.com/setting-up-multiple-ios-devices-for-messages-and-facetime.htm l
FaceTime and iMessage not accepting Apple ID password
http://www.ilounge.com/index.php/articles/comments/facetime-and-imessage-not-acc epting-apple-id-password/
Unable to use FaceTime and iMessage with my apple ID
https://discussions.apple.com/thread/4649373?tstart=90
 Cheers, Tom

I paid for exportpdf and everytime i try to use tool on pdf, it asks me to subscribe. i have to log into website EVERY time. not acceptable. how can i export only form fields that were filled in?

i paid for exportpdf and every time i try to use tool on pdf, it asks me to subscribe. i have to log into website EVERY time. not acceptable. Some forms can't be saved so having to log in and only use webtool to upload a saved pdf won't work.
as well, how can i export only form fields that were filled in if I can get pdf to save to computer?

Hi kstine,
I can see why that would be frustrating! Have you tried selecting Stayed Signed In underneath the Adobe ID and Password boxes when you try to log in?
What did you use to create the PDF form? If you used FormsCentral, form data is saved to your online FormsCentral account. If you have Acrobat, you can export form data as described here: Adobe Acrobat X Pro * Manage form data files
Best,
Sara

HT3775 how can i write visual basic programs on my mac? and what IDE do i use? My mac runs on OS X mavericks.

please help

Install MS Windows as a Virtual Machine guest operating system on your Mac. You will want a minimum of 8GB memory. Popular VM are VirtualBox, Parallels, and VMware. Once this is done, you can download the Microsoft Visual Studio 2013 development environment into WIndows 7 in the VM, and use it there.

How do I import a personal DVD into iDVD for editing and copying

I am running 10.9.5. I see that I have 2.66 GHZ Intel Core 2 Duo with 4 GB of memory
Do I have enough power on this machine to even do what I want to do?
I have several DVD's of home movies that have been digitized.
The files on the DVD list Video_rm and Video_ts. I see a place to import this DVD, but I am not able to select both folders to import at the same time.
What do I need to do in order to edit these home movies on my computer?
thanks,

Here is how I do it, with no quality loss that I can see. (And I'm picky.)
Use Cinematize 2, I use it with iMovie 06 (and a few times with iMovie 11) and iDVD 11. It has several modes of converting the data. One mode is called "lossless".
http://www.amazon.com/Miraizon-10121201-Cinematize-2-Mac/dp/B0006AAO96/ref=cm_cr _pr_pb_t
I would use iMovie 06 with iDVD 09 - 11, why?
iMovie 09/11 uses 'single field processing' meaning every other horizontal line of the video is thrown out, which reduces the sharpness of the footage. iMovie 06 uses ALL of the image to form the video.
 Cinematize 2 + iMovie 06 + iDVD 09/11 works great for me.
Use Professional Quality in iDVD, good for 2 Hrs on a single layer DVD, 3 Hrs 45 Mins on a Dual layer DVD. I use DVD+Rs only.

How to create this code in labview

hello...
please helpe me for this Question
i have create this code "c" in " labview "...
ex c :
if portc.f1==1 {
portc.f0=~portc.f0
ex labview :
if push button ==1 {
round led =~ round led
thanks...
Solved!
Go to Solution.

pjr1121 wrote:
See attached image.
Why do people insist on using property nodes to get the value. It has the same issues with race conditions as the local variable but is extremely slow (forces a thread swap to the UI thread). Besides, you should be keeping the value of the LED in a shift register.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines
Attachments:
Toggle LED.png ‏16 KB

How do i develop code in LabVIEW 7.1 for configuring and performing gated edge counting using NI-DAQmx

Similar Messages

Maybe you are looking for