How to generate an IP core from an available Verilog code ?

Question

Hi everyone,
Currently, I would like to test a Active Noise Cancellation (ANC) system on Zedboard. This system consist of a ANC Chip embedded inside FPGA and written by Verilog language and a earphone which includes a microphone and loudspeaker. This means we need to use ADAU1761 Chip for testing on Zedboard. I also have studied and known that in order to use and control this Audio Chip by writing Verilog code is so difficult.I also referred Lab4 on Xilinx website and I understand that my problem can be solved by synthesizing an IP core from Verilog (which I am programming for ANC chip) as FIR filter in Lab4. My biggest problem, I don't know how to generate an IP core from my Verilog code and I also don't know any tools can help me solve this problem.
Please kindly let me know the way to generate an IP core from my Verilog code or  the tools I can use for this problem. Any your suggestions to solve this problem are  significant with me.
Thanks in advance !

Answer 1

h,
I would start reading the users guides, and reference manuals.  I would work example through the tools.
An IP block is nothing but a verilog or VHDL block that you decide to use over again.  Once your block is working, the tools (ISE or Vivado) allow you to capture it, and encapsulate it as an IP block that can be re-used later in other projects (it becomes a library function).
So, first get it to work.  Then worry about making it an IP block, and then, only if you need to use it again and again in other projects.  If not, then there is no need to go to the trouble of making it an IP block -- just use the verilog or VHDL whenever you need it.